1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung's Exynos USI (Universal Serial Interface) binding
10 - Sam Protsenko <semen.protsenko@linaro.org>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
15 USI shares almost all internal circuits within each protocol, so only one
16 protocol can be chosen at a time. USI is modeled as a node with zero or more
17 child nodes, each representing a serial sub-node device. The mode setting
18 selects which particular function will be used.
22 pattern: "^usi@[0-9a-f]+$"
27 - const: samsung,exynosautov9-usi
28 - const: samsung,exynos850-usi
30 - samsung,exynos850-usi
47 $ref: /schemas/types.yaml#/definitions/phandle-array
50 - description: phandle to System Register syscon node
51 - description: offset of SW_CONF register for this USI controller
53 Should be phandle/offset pair. The phandle to System Register syscon node
54 (for the same domain where this USI controller resides) and the offset
55 of SW_CONF register for this USI controller.
58 $ref: /schemas/types.yaml#/definitions/uint32
60 Selects USI function (which serial protocol to use). Refer to
61 <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
66 Enable this property if underlying protocol requires the clock to be
67 continuously provided without automatic gating. As suggested by SoC
68 manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
69 multi-master mode. Usually this property is needed if USI mode is set
72 This property is optional.
76 $ref: /schemas/i2c/i2c-exynos5.yaml
77 description: Child node describing underlying I2C
80 $ref: /schemas/serial/samsung_uart.yaml
81 description: Child node describing underlying UART/serial
84 $ref: /schemas/spi/samsung,spi.yaml
85 description: Child node describing underlying SPI
100 - samsung,exynos850-usi
109 - description: Bus (APB) clock
110 - description: Operating clock for UART/SPI/I2C protocol
127 samsung,clkreq-on: false
129 additionalProperties: false
133 #include <dt-bindings/interrupt-controller/arm-gic.h>
134 #include <dt-bindings/soc/samsung,exynos-usi.h>
137 compatible = "samsung,exynos850-usi";
138 reg = <0x138200c0 0x20>;
139 samsung,sysreg = <&sysreg_peri 0x1010>;
140 samsung,mode = <USI_V2_UART>;
141 samsung,clkreq-on; /* needed for UART mode */
142 #address-cells = <1>;
145 clocks = <&cmu_peri 32>, <&cmu_peri 31>;
146 clock-names = "pclk", "ipclk";
148 serial_0: serial@13820000 {
149 compatible = "samsung,exynos850-uart";
150 reg = <0x13820000 0xc0>;
151 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&cmu_peri 32>, <&cmu_peri 31>;
153 clock-names = "uart", "clk_uart_baud0";
157 hsi2c_0: i2c@13820000 {
158 compatible = "samsung,exynosautov9-hsi2c";
159 reg = <0x13820000 0xc0>;
160 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
161 #address-cells = <1>;
163 clocks = <&cmu_peri 31>, <&cmu_peri 32>;
164 clock-names = "hsi2c", "hsi2c_pclk";