1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,smsm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Shared Memory State Machine
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 The Shared Memory State Machine facilitates broadcasting of single bit state
16 information between the processors in a Qualcomm SoC. Each processor is
17 assigned 32 bits of state that can be modified. A processor can through a
18 matrix of bitmaps signal subscription of notifications upon changes to a
19 certain bit owned by a certain remote processor.
29 $ref: /schemas/types.yaml#/definitions/uint32
32 Identifier of the local processor in the list of hosts, or in other words
33 specifier of the column in the subscription matrix representing the local
41 $ref: /schemas/types.yaml#/definitions/phandle-array
44 - description: phandle to a syscon node representing the APCS registers
45 - description: u32 representing offset to the register within the syscon
46 - description: u32 representing the ipc bit within the register
48 Three entries specifying the outgoing ipc bit used for signaling the N:th
54 Each processor's state bits are described by a subnode of the SMSM device
55 node. Nodes can either be flagged as an interrupt-controller to denote a
56 remote processor's state bits or the local processors bits. The node
57 names are not important.
65 Marks the entry as a interrupt-controller and the state bits to
66 belong to a remote processor.
74 One entry specifying remote IRQ used by the remote processor to
75 signal changes of its state bits.
77 '#qcom,smem-state-cells':
78 $ref: /schemas/types.yaml#/definitions/uint32
81 Required for local entry. Denotes bit number.
88 - '#qcom,smem-state-cells'
90 - interrupt-controller
94 additionalProperties: false
111 additionalProperties: false
114 # The following example shows the SMEM setup for controlling properties of
115 # the wireless processor, defined from the 8974 apps processor's
116 # point-of-view. It encompasses one outbound entry and the outgoing interrupt
117 # for the wireless processor.
119 #include <dt-bindings/interrupt-controller/arm-gic.h>
122 compatible = "qcom,smsm";
123 #address-cells = <1>;
125 qcom,ipc-3 = <&apcs 8 19>;
129 #qcom,smem-state-cells = <1>;
132 wcnss_smsm: wcnss@7 {
134 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
135 interrupt-controller;
136 #interrupt-cells = <2>;