1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,gsbi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm General Serial Bus Interface (GSBI)
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 The GSBI controller is modeled as a node with zero or more child nodes, each
16 representing a serial sub-node device that is mux'd as part of the GSBI
17 configuration settings. The mode setting will govern the input/output mode
20 A GSBI controller node can contain 0 or more child nodes representing serial
21 devices. These serial devices can be a QCOM UART, I2C controller, spi
22 controller, or some combination of aforementioned devices.
26 const: qcom,gsbi-v1.0.0
32 $ref: /schemas/types.yaml#/definitions/uint32
43 $ref: /schemas/types.yaml#/definitions/uint32
45 CRCI MUX value for QUP CRCI ports. Please reference
46 include/dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
49 $ref: /schemas/types.yaml#/definitions/uint32
51 MUX value for configuration of the serial interface. Please reference
52 include/dt-bindings/soc/qcom,gsbi.h for valid mux values.
58 $ref: /schemas/types.yaml#/definitions/phandle
60 Phandle of TCSR syscon node.Required if child uses dma.
70 $ref: /schemas/spi/qcom,spi-qup.yaml#
74 $ref: /schemas/i2c/qcom,i2c-qup.yaml#
78 $ref: /schemas/serial/qcom,msm-uartdm.yaml#
88 additionalProperties: false
92 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
93 #include <dt-bindings/interrupt-controller/arm-gic.h>
94 #include <dt-bindings/soc/qcom,gsbi.h>
97 compatible = "qcom,gsbi-v1.0.0";
98 reg = <0x12440000 0x100>;
100 clocks = <&gcc GSBI1_H_CLK>;
101 clock-names = "iface";
102 #address-cells = <1>;
106 syscon-tcsr = <&tcsr>;
107 qcom,mode = <GSBI_PROT_I2C_UART>;
110 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
111 reg = <0x12450000 0x100>,
113 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
115 clock-names = "core", "iface";
119 compatible = "qcom,i2c-qup-v1.1.1";
120 reg = <0x12460000 0x1000>;
121 pinctrl-0 = <&i2c1_pins>;
122 pinctrl-1 = <&i2c1_pins_sleep>;
123 pinctrl-names = "default", "sleep";
124 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
126 clock-names = "core", "iface";
127 #address-cells = <1>;
130 status = "disabled"; /* UART chosen */