1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GENI Serial Engine QUP Wrapper Controller
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
14 is a programmable module for supporting a wide range of serial interfaces
15 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
16 Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
17 Wrapper controller is modeled as a node with zero or more child nodes each
18 representing a serial engine.
24 - qcom,geni-se-i2c-master-hub
27 description: QUP wrapper common register address and length.
69 description: GENI serial engine based SPI controller. SPI in master mode
70 supports up to 50MHz, up to four chip selects, programmable
71 data path from 4 bits to 32 bits and numerous protocol
73 $ref: /schemas/spi/qcom,spi-geni-qcom.yaml#
77 description: GENI serial engine based I2C controller.
78 $ref: /schemas/i2c/qcom,i2c-geni-qcom.yaml#
82 description: GENI Serial Engine based UART Controller.
83 $ref: /schemas/serial/qcom,serial-geni-qcom.yaml#
90 const: qcom,geni-se-i2c-master-hub
99 - description: Slave AHB Clock
104 "spi@[0-9a-f]+$": false
105 "serial@[0-9a-f]+$": false
115 - description: Master AHB Clock
116 - description: Slave AHB Clock
118 additionalProperties: false
122 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
123 #include <dt-bindings/interrupt-controller/arm-gic.h>
126 #address-cells = <2>;
130 compatible = "qcom,geni-se-qup";
131 reg = <0 0x008c0000 0 0x6000>;
132 clock-names = "m-ahb", "s-ahb";
133 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
134 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
135 #address-cells = <2>;
140 compatible = "qcom,geni-i2c";
141 reg = <0 0xa94000 0 0x4000>;
142 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
145 pinctrl-names = "default", "sleep";
146 pinctrl-0 = <&qup_1_i2c_5_active>;
147 pinctrl-1 = <&qup_1_i2c_5_sleep>;
148 #address-cells = <1>;
152 uart0: serial@a88000 {
153 compatible = "qcom,geni-uart";
154 reg = <0 0xa88000 0 0x7000>;
155 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
158 pinctrl-names = "default", "sleep";
159 pinctrl-0 = <&qup_1_uart_3_active>;
160 pinctrl-1 = <&qup_1_uart_3_sleep>;