Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
   5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   6
   7 title: GENI Serial Engine QUP Wrapper Controller
   8
   9 maintainers:
  10   - Bjorn Andersson <bjorn.andersson@linaro.org>
  11
  12 description: |
  13  Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
  14  is a programmable module for supporting a wide range of serial interfaces
  15  like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
  16  Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
  17  Wrapper controller is modeled as a node with zero or more child nodes each
  18  representing a serial engine.
  19
  20 properties:
  21   compatible:
  22     enum:
  23       - qcom,geni-se-qup
  24
  25   reg:
  26     description: QUP wrapper common register address and length.
  27     maxItems: 1
  28
  29   clock-names:
  30     items:
  31       - const: m-ahb
  32       - const: s-ahb
  33
  34   clocks:
  35     items:
  36       - description: Master AHB Clock
  37       - description: Slave AHB Clock
  38
  39   "#address-cells":
  40     const: 2
  41
  42   "#size-cells":
  43     const: 2
  44
  45   ranges: true
  46
  47   interconnects:
  48     maxItems: 1
  49
  50   interconnect-names:
  51     const: qup-core
  52
  53   iommus:
  54     maxItems: 1
  55
  56 required:
  57   - compatible
  58   - reg
  59   - clock-names
  60   - clocks
  61   - "#address-cells"
  62   - "#size-cells"
  63   - ranges
  64
  65 patternProperties:
  66   "spi@[0-9a-f]+$":
  67     type: object
  68     description: GENI serial engine based SPI controller. SPI in master mode
  69                  supports up to 50MHz, up to four chip selects, programmable
  70                  data path from 4 bits to 32 bits and numerous protocol
  71                  variants.
  72     $ref: /schemas/spi/qcom,spi-geni-qcom.yaml#
  73
  74   "i2c@[0-9a-f]+$":
  75     type: object
  76     description: GENI serial engine based I2C controller.
  77     $ref: /schemas/i2c/qcom,i2c-geni-qcom.yaml#
  78
  79   "serial@[0-9a-f]+$":
  80     type: object
  81     description: GENI Serial Engine based UART Controller.
  82     $ref: /schemas/serial/qcom,serial-geni-qcom.yaml#
  83
  84 additionalProperties: false
  85
  86 examples:
  87   - |
  88     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  89     #include <dt-bindings/interrupt-controller/arm-gic.h>
  90
  91     soc {
  92         #address-cells = <2>;
  93         #size-cells = <2>;
  94
  95         geniqup@8c0000 {
  96             compatible = "qcom,geni-se-qup";
  97             reg = <0 0x008c0000 0 0x6000>;
  98             clock-names = "m-ahb", "s-ahb";
  99             clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 100                 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 101             #address-cells = <2>;
 102             #size-cells = <2>;
 103             ranges;
 104
 105             i2c0: i2c@a94000 {
 106                 compatible = "qcom,geni-i2c";
 107                 reg = <0 0xa94000 0 0x4000>;
 108                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 109                 clock-names = "se";
 110                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 111                 pinctrl-names = "default", "sleep";
 112                 pinctrl-0 = <&qup_1_i2c_5_active>;
 113                 pinctrl-1 = <&qup_1_i2c_5_sleep>;
 114                 #address-cells = <1>;
 115                 #size-cells = <0>;
 116             };
 117
 118             uart0: serial@a88000 {
 119                 compatible = "qcom,geni-uart";
 120                 reg = <0 0xa88000 0 0x7000>;
 121                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 122                 clock-names = "se";
 123                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 124                 pinctrl-names = "default", "sleep";
 125                 pinctrl-0 = <&qup_1_uart_3_active>;
 126                 pinctrl-1 = <&qup_1_uart_3_sleep>;
 127             };
 128         };
 129     };
 130
 131 ...