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[releases.git] / Documentation / devicetree / bindings / soc / mediatek / mediatek,ccorr.yaml
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MediaTek color correction
8
9 maintainers:
10   - Matthias Brugger <matthias.bgg@gmail.com>
11   - Moudy Ho <moudy.ho@mediatek.com>
12
13 description: |
14   MediaTek color correction with 3X3 matrix.
15
16 properties:
17   compatible:
18     items:
19       - enum:
20           - mediatek,mt8183-mdp3-ccorr
21
22   reg:
23     maxItems: 1
24
25   mediatek,gce-client-reg:
26     $ref: /schemas/types.yaml#/definitions/phandle-array
27     items:
28       items:
29         - description: phandle of GCE
30         - description: GCE subsys id
31         - description: register offset
32         - description: register size
33     description: The register of client driver can be configured by gce with
34       4 arguments defined in this property. Each GCE subsys id is mapping to
35       a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
36
37   mediatek,gce-events:
38     description:
39       The event id which is mapping to the specific hardware event signal
40       to gce. The event id is defined in the gce header
41       include/dt-bindings/gce/<chip>-gce.h of each chips.
42     $ref: /schemas/types.yaml#/definitions/uint32-array
43
44   clocks:
45     minItems: 1
46
47 required:
48   - compatible
49   - reg
50   - mediatek,gce-client-reg
51   - mediatek,gce-events
52   - clocks
53
54 additionalProperties: false
55
56 examples:
57   - |
58     #include <dt-bindings/clock/mt8183-clk.h>
59     #include <dt-bindings/gce/mt8183-gce.h>
60
61     mdp3_ccorr: mdp3-ccorr@1401c000 {
62       compatible = "mediatek,mt8183-mdp3-ccorr";
63       reg = <0x1401c000 0x1000>;
64       mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
65       mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>,
66                             <CMDQ_EVENT_MDP_CCORR_EOF>;
67       clocks = <&mmsys CLK_MM_MDP_CCORR>;
68     };