Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: NXP i.MX8MP Media Block Control
   8
   9 maintainers:
  10   - Paul Elder <paul.elder@ideasonboard.com>
  11
  12 description:
  13   The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
  14   providing access to the NoC and ensuring proper power sequencing of the
  15   peripherals within the MEDIAMIX domain.
  16
  17 properties:
  18   compatible:
  19     items:
  20       - const: fsl,imx8mp-media-blk-ctrl
  21       - const: syscon
  22
  23   reg:
  24     maxItems: 1
  25
  26   '#address-cells':
  27     const: 1
  28
  29   '#size-cells':
  30     const: 1
  31
  32   '#power-domain-cells':
  33     const: 1
  34
  35   power-domains:
  36     maxItems: 10
  37
  38   power-domain-names:
  39     items:
  40       - const: bus
  41       - const: mipi-dsi1
  42       - const: mipi-csi1
  43       - const: lcdif1
  44       - const: isi
  45       - const: mipi-csi2
  46       - const: lcdif2
  47       - const: isp
  48       - const: dwe
  49       - const: mipi-dsi2
  50
  51   clocks:
  52     items:
  53       - description: The APB clock
  54       - description: The AXI clock
  55       - description: The pixel clock for the first CSI2 receiver (aclk)
  56       - description: The pixel clock for the second CSI2 receiver (aclk)
  57       - description: The pixel clock for the first LCDIF (pix_clk)
  58       - description: The pixel clock for the second LCDIF (pix_clk)
  59       - description: The core clock for the ISP (clk)
  60       - description: The MIPI-PHY reference clock used by DSI
  61
  62   clock-names:
  63     items:
  64       - const: apb
  65       - const: axi
  66       - const: cam1
  67       - const: cam2
  68       - const: disp1
  69       - const: disp2
  70       - const: isp
  71       - const: phy
  72
  73   interconnects:
  74     maxItems: 8
  75
  76   interconnect-names:
  77     items:
  78       - const: lcdif-rd
  79       - const: lcdif-wr
  80       - const: isi0
  81       - const: isi1
  82       - const: isi2
  83       - const: isp0
  84       - const: isp1
  85       - const: dwe
  86
  87   bridge@5c:
  88     type: object
  89     $ref: /schemas/display/bridge/fsl,ldb.yaml#
  90     unevaluatedProperties: false
  91
  92 required:
  93   - compatible
  94   - reg
  95   - '#address-cells'
  96   - '#size-cells'
  97   - '#power-domain-cells'
  98   - power-domains
  99   - power-domain-names
 100   - clocks
 101   - clock-names
 102
 103 additionalProperties: false
 104
 105 examples:
 106   - |
 107     #include <dt-bindings/clock/imx8mp-clock.h>
 108     #include <dt-bindings/power/imx8mp-power.h>
 109
 110     blk-ctrl@32ec0000 {
 111         compatible = "fsl,imx8mp-media-blk-ctrl", "syscon";
 112         reg = <0x32ec0000 0x138>;
 113         power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>,
 114                         <&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>,
 115                         <&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>,
 116                         <&mipi_phy2_pd>;
 117         power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
 118                              "mipi-csi2", "lcdif2", "isp", "dwe", "mipi-dsi2";
 119         clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
 120                  <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
 121                  <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
 122                  <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
 123                  <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
 124                  <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
 125                  <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
 126                  <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
 127         clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2",
 128                       "isp", "phy";
 129         #power-domain-cells = <1>;
 130         #address-cells = <1>;
 131         #size-cells = <1>;
 132
 133         bridge@5c {
 134             compatible = "fsl,imx8mp-ldb";
 135             reg = <0x5c 0x4>, <0x128 0x4>;
 136             reg-names = "ldb", "lvds";
 137             clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
 138             clock-names = "ldb";
 139
 140             ports {
 141                 #address-cells = <1>;
 142                 #size-cells = <0>;
 143
 144                 port@0 {
 145                     reg = <0>;
 146
 147                     ldb_from_lcdif2: endpoint {
 148                         remote-endpoint = <&lcdif2_to_ldb>;
 149                     };
 150                 };
 151
 152                 port@1 {
 153                     reg = <1>;
 154
 155                     ldb_lvds_ch0: endpoint {
 156                         remote-endpoint = <&ldb_to_lvdsx4panel>;
 157                     };
 158                 };
 159
 160                 port@2 {
 161                     reg = <2>;
 162
 163                     ldb_lvds_ch1: endpoint {
 164                     };
 165                 };
 166             };
 167         };
 168     };
 169 ...