1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP Media Block Control
10 - Paul Elder <paul.elder@ideasonboard.com>
13 The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
14 providing access to the NoC and ensuring proper power sequencing of the
15 peripherals within the MEDIAMIX domain.
20 - const: fsl,imx8mp-media-blk-ctrl
26 '#power-domain-cells':
47 - description: The APB clock
48 - description: The AXI clock
49 - description: The pixel clock for the first CSI2 receiver (aclk)
50 - description: The pixel clock for the second CSI2 receiver (aclk)
51 - description: The pixel clock for the first LCDIF (pix_clk)
52 - description: The pixel clock for the second LCDIF (pix_clk)
53 - description: The core clock for the ISP (clk)
54 - description: The MIPI-PHY reference clock used by DSI
84 - '#power-domain-cells'
90 additionalProperties: false
94 #include <dt-bindings/clock/imx8mp-clock.h>
95 #include <dt-bindings/power/imx8mp-power.h>
97 media_blk_ctl: blk-ctl@32ec0000 {
98 compatible = "fsl,imx8mp-media-blk-ctrl", "syscon";
99 reg = <0x32ec0000 0x138>;
100 power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>,
101 <&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>,
102 <&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>,
104 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
105 "mipi-csi2", "lcdif2", "isp", "dwe", "mipi-dsi2";
106 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
107 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
108 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
109 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
110 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
111 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
112 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
113 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
114 clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2",
116 #power-domain-cells = <1>;