1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM VPU blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the VPU peripherals
15 located in the VPU domain of the SoC.
20 - const: fsl,imx8mm-vpu-blk-ctrl
26 '#power-domain-cells':
60 const: fsl,imx8mm-vpu-blk-ctrl
65 - description: bus power domain
66 - description: G1 decoder power domain
67 - description: G2 decoder power domain
68 - description: H1 encoder power domain
79 - description: G1 decoder clk
80 - description: G2 decoder clk
81 - description: H1 encoder clk
91 - description: G1 decoder interconnect
92 - description: G2 decoder interconnect
93 - description: H1 encoder power domain
105 const: fsl,imx8mp-vpu-blk-ctrl
110 - description: bus power domain
111 - description: G1 decoder power domain
112 - description: G2 decoder power domain
113 - description: VC8000E encoder power domain
124 - description: G1 decoder clk
125 - description: G2 decoder clk
126 - description: VC8000E encoder clk
136 - description: G1 decoder interconnect
137 - description: G2 decoder interconnect
138 - description: VC8000E encoder interconnect
146 additionalProperties: false
150 #include <dt-bindings/clock/imx8mm-clock.h>
151 #include <dt-bindings/power/imx8mm-power.h>
153 vpu_blk_ctrl: blk-ctrl@38330000 {
154 compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
155 reg = <0x38330000 0x100>;
156 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
157 <&pgc_vpu_g2>, <&pgc_vpu_h1>;
158 power-domain-names = "bus", "g1", "g2", "h1";
159 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
160 <&clk IMX8MM_CLK_VPU_G2_ROOT>,
161 <&clk IMX8MM_CLK_VPU_H1_ROOT>;
162 clock-names = "g1", "g2", "h1";
163 #power-domain-cells = <1>;