1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
15 peripherals located in the DISP domain of the SoC.
20 - const: fsl,imx8mm-disp-blk-ctrl
26 '#power-domain-cells':
47 - const: csi-bridge-axi
48 - const: csi-bridge-apb
49 - const: csi-bridge-core
66 additionalProperties: false
70 #include <dt-bindings/clock/imx8mm-clock.h>
71 #include <dt-bindings/power/imx8mm-power.h>
73 disp_blk_ctl: blk_ctrl@32e28000 {
74 compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
75 reg = <0x32e28000 0x100>;
76 power-domains = <&pgc_dispmix>, <&pgc_dispmix>, <&pgc_dispmix>,
77 <&pgc_mipi>, <&pgc_mipi>;
78 power-domain-names = "bus", "csi-bridge", "lcdif",
79 "mipi-dsi", "mipi-csi";
80 clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
81 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
82 <&clk IMX8MM_CLK_CSI1_ROOT>,
83 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
84 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
85 <&clk IMX8MM_CLK_DISP_ROOT>,
86 <&clk IMX8MM_CLK_DSI_CORE>,
87 <&clk IMX8MM_CLK_DSI_PHY_REF>,
88 <&clk IMX8MM_CLK_CSI1_CORE>,
89 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
90 clock-names = "csi-bridge-axi", "csi-bridge-apb", "csi-bridge-core",
91 "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
92 "dsi-ref", "csi-aclk", "csi-pclk";
93 #power-domain-cells = <1>;