1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/serial/samsung_uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
16 decimal integer) as specified by User's Manual of respective SoC.
23 - samsung,s3c2410-uart
24 - samsung,s3c2412-uart
25 - samsung,s3c2440-uart
26 - samsung,s3c6400-uart
27 - samsung,s5pv210-uart
28 - samsung,exynos4210-uart
35 The size (in bytes) of the IO accesses that should be performed
37 $ref: /schemas/types.yaml#/definitions/uint32
45 description: N = 0 is allowed for SoCs without internal baud clock mux.
49 - pattern: '^clk_uart_baud[0-3]$'
50 - pattern: '^clk_uart_baud[0-3]$'
51 - pattern: '^clk_uart_baud[0-3]$'
52 - pattern: '^clk_uart_baud[0-3]$'
56 - description: DMA controller phandle and request line for RX
57 - description: DMA controller phandle and request line for TX
65 description: RX interrupt and optionally TX interrupt.
69 samsung,uart-fifosize:
70 description: The fifo size supported by the UART channel.
71 $ref: /schemas/types.yaml#/definitions/uint32
81 unevaluatedProperties: false
91 - samsung,s3c2410-uart
92 - samsung,s5pv210-uart
103 - pattern: '^clk_uart_baud[0-1]$'
104 - pattern: '^clk_uart_baud[0-1]$'
112 - samsung,exynos4210-uart
123 - const: clk_uart_baud0
127 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
129 uart0: serial@7f005000 {
130 compatible = "samsung,s3c6400-uart";
131 reg = <0x7f005000 0x100>;
132 interrupt-parent = <&vic1>;
134 clock-names = "uart", "clk_uart_baud2",
136 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
138 samsung,uart-fifosize = <16>;