1 # Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
4 $id: http://devicetree.org/schemas/serial/8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART (Universal Asynchronous Receiver/Transmitter) bindings
10 - devicetree@vger.kernel.org
19 - aspeed,lpc-interrupts
21 - aspeed,sirq-polarity-sense
25 const: aspeed,ast2500-vuart
48 - required: [ clock-frequency ]
49 - required: [ clocks ]
59 - const: aspeed,ast2400-vuart
60 - const: aspeed,ast2500-vuart
61 - const: intel,xscale-uart
62 - const: mrvl,pxa-uart
63 - const: nuvoton,wpcm450-uart
64 - const: nuvoton,npcm750-uart
65 - const: nuvoton,npcm845-uart
66 - const: nvidia,tegra20-uart
67 - const: nxp,lpc3220-uart
83 - opencores,uart16550-rtlsvn105
89 - cavium,octeon-3860-uart
90 - xlnx,xps-uart16550-2.00.b
93 - ns16550 # Deprecated, unless the FIFO really is broken
100 - const: ralink,rt2880-uart
102 - ns16550 # Deprecated, unless the FIFO really is broken
106 - mediatek,mt7622-btif
107 - mediatek,mt7623-btif
108 - const: mediatek,mtk-btif
110 - const: mrvl,mmp-uart
111 - const: intel,xscale-uart
114 - nvidia,tegra30-uart
115 - nvidia,tegra114-uart
116 - nvidia,tegra124-uart
117 - nvidia,tegra210-uart
118 - nvidia,tegra186-uart
119 - nvidia,tegra194-uart
120 - nvidia,tegra234-uart
121 - const: nvidia,tegra20-uart
129 clock-frequency: true
138 $ref: /schemas/types.yaml#/definitions/uint32
139 description: The current active speed of the UART.
142 $ref: /schemas/types.yaml#/definitions/uint32
144 Offset to apply to the mapbase from the start of the registers.
147 description: Quantity to shift the register offsets by.
151 The size (in bytes) of the IO accesses that should be performed on the
152 device. There are some systems that require 32-bit accesses to the
153 UART (e.g. TI davinci).
158 Set to indicate that the port is in use by the OpenFirmware RTAS and
159 should not be registered.
164 Set to indicate that the port does not implement loopback test mode.
167 $ref: /schemas/types.yaml#/definitions/uint32
168 description: The fifo size of the UART.
173 One way to enable automatic flow control support. The driver is
174 allowed to detect support for the capability even without this
179 Specify the TX FIFO low water indication for parts with programmable
184 How long to pause uart rx when input overrun is encountered.
193 aspeed,sirq-polarity-sense:
194 $ref: /schemas/types.yaml#/definitions/phandle-array
196 Phandle to aspeed,ast2500-scu compatible syscon alongside register
197 offset and bit number to identify how the SIRQ polarity should be
198 configured. One possible data source is the LPC/eSPI mode bit. Only
199 applicable to aspeed,ast2500-vuart.
203 $ref: '/schemas/types.yaml#/definitions/uint32'
205 The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
207 aspeed,lpc-interrupts:
208 $ref: "/schemas/types.yaml#/definitions/uint32-array"
212 A 2-cell property describing the VUART SIRQ number and SIRQ
213 polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only
214 applicable to aspeed,ast2500-vuart.
220 unevaluatedProperties: false
225 compatible = "ns8250";
226 reg = <0x80230000 0x100>;
229 clock-frequency = <48000000>;
232 #include <dt-bindings/gpio/gpio.h>
234 compatible = "andestech,uart16550", "ns16550a";
235 reg = <0x49042000 0x400>;
237 clock-frequency = <48000000>;
238 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
239 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
240 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
241 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
242 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
243 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
246 #include <dt-bindings/clock/aspeed-clock.h>
247 #include <dt-bindings/interrupt-controller/irq.h>
249 compatible = "aspeed,ast2500-vuart";
250 reg = <0x1e787000 0x40>;
253 clocks = <&syscon ASPEED_CLK_APB>;
255 aspeed,lpc-io-reg = <0x3f8>;
256 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;