Documentation/devicetree/bindings/serial/8250.yaml

   1 # Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/serial/8250.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: UART (Universal Asynchronous Receiver/Transmitter) bindings
   8
   9 maintainers:
  10   - devicetree@vger.kernel.org
  11
  12 allOf:
  13   - $ref: serial.yaml#
  14   - if:
  15       anyOf:
  16         - required:
  17             - aspeed,lpc-io-reg
  18         - required:
  19             - aspeed,lpc-interrupts
  20         - required:
  21             - aspeed,sirq-polarity-sense
  22     then:
  23       properties:
  24         compatible:
  25           const: aspeed,ast2500-vuart
  26   - if:
  27       properties:
  28         compatible:
  29           const: mrvl,mmp-uart
  30     then:
  31       properties:
  32         reg-shift:
  33           const: 2
  34       required:
  35         - reg-shift
  36   - if:
  37       not:
  38         properties:
  39           compatible:
  40             items:
  41               - enum:
  42                   - ns8250
  43                   - ns16450
  44                   - ns16550
  45                   - ns16550a
  46     then:
  47       anyOf:
  48         - required: [ clock-frequency ]
  49         - required: [ clocks ]
  50
  51 properties:
  52   compatible:
  53     oneOf:
  54       - const: ns8250
  55       - const: ns16450
  56       - const: ns16550
  57       - const: ns16550a
  58       - const: ns16850
  59       - const: aspeed,ast2400-vuart
  60       - const: aspeed,ast2500-vuart
  61       - const: intel,xscale-uart
  62       - const: mrvl,pxa-uart
  63       - const: nuvoton,wpcm450-uart
  64       - const: nuvoton,npcm750-uart
  65       - const: nuvoton,npcm845-uart
  66       - const: nvidia,tegra20-uart
  67       - const: nxp,lpc3220-uart
  68       - items:
  69           - enum:
  70               - exar,xr16l2552
  71               - exar,xr16l2551
  72               - exar,xr16l2550
  73           - const: ns8250
  74       - items:
  75           - enum:
  76               - altr,16550-FIFO32
  77               - altr,16550-FIFO64
  78               - altr,16550-FIFO128
  79               - fsl,16550-FIFO64
  80               - fsl,ns16550
  81               - andestech,uart16550
  82               - nxp,lpc1850-uart
  83               - opencores,uart16550-rtlsvn105
  84               - ti,da830-uart
  85           - const: ns16550a
  86       - items:
  87           - enum:
  88               - ns16750
  89               - cavium,octeon-3860-uart
  90               - xlnx,xps-uart16550-2.00.b
  91               - ralink,rt2880-uart
  92           - enum:
  93               - ns16550 # Deprecated, unless the FIFO really is broken
  94               - ns16550a
  95       - items:
  96           - enum:
  97               - ralink,mt7620a-uart
  98               - ralink,rt3052-uart
  99               - ralink,rt3883-uart
 100           - const: ralink,rt2880-uart
 101           - enum:
 102               - ns16550 # Deprecated, unless the FIFO really is broken
 103               - ns16550a
 104       - items:
 105           - enum:
 106               - mediatek,mt7622-btif
 107               - mediatek,mt7623-btif
 108           - const: mediatek,mtk-btif
 109       - items:
 110           - const: mrvl,mmp-uart
 111           - const: intel,xscale-uart
 112       - items:
 113           - enum:
 114               - nvidia,tegra30-uart
 115               - nvidia,tegra114-uart
 116               - nvidia,tegra124-uart
 117               - nvidia,tegra210-uart
 118               - nvidia,tegra186-uart
 119               - nvidia,tegra194-uart
 120               - nvidia,tegra234-uart
 121           - const: nvidia,tegra20-uart
 122
 123   reg:
 124     maxItems: 1
 125
 126   interrupts:
 127     maxItems: 1
 128
 129   clock-frequency: true
 130
 131   clocks:
 132     maxItems: 1
 133
 134   resets:
 135     maxItems: 1
 136
 137   current-speed:
 138     $ref: /schemas/types.yaml#/definitions/uint32
 139     description: The current active speed of the UART.
 140
 141   reg-offset:
 142     $ref: /schemas/types.yaml#/definitions/uint32
 143     description: |
 144       Offset to apply to the mapbase from the start of the registers.
 145
 146   reg-shift:
 147     description: Quantity to shift the register offsets by.
 148
 149   reg-io-width:
 150     description: |
 151       The size (in bytes) of the IO accesses that should be performed on the
 152       device. There are some systems that require 32-bit accesses to the
 153       UART (e.g. TI davinci).
 154
 155   used-by-rtas:
 156     type: boolean
 157     description: |
 158       Set to indicate that the port is in use by the OpenFirmware RTAS and
 159       should not be registered.
 160
 161   no-loopback-test:
 162     type: boolean
 163     description: |
 164       Set to indicate that the port does not implement loopback test mode.
 165
 166   fifo-size:
 167     $ref: /schemas/types.yaml#/definitions/uint32
 168     description: The fifo size of the UART.
 169
 170   auto-flow-control:
 171     type: boolean
 172     description: |
 173       One way to enable automatic flow control support. The driver is
 174       allowed to detect support for the capability even without this
 175       property.
 176
 177   tx-threshold:
 178     description: |
 179       Specify the TX FIFO low water indication for parts with programmable
 180       TX FIFO thresholds.
 181
 182   overrun-throttle-ms:
 183     description: |
 184       How long to pause uart rx when input overrun is encountered.
 185
 186   rts-gpios: true
 187   cts-gpios: true
 188   dtr-gpios: true
 189   dsr-gpios: true
 190   rng-gpios: true
 191   dcd-gpios: true
 192
 193   aspeed,sirq-polarity-sense:
 194     $ref: /schemas/types.yaml#/definitions/phandle-array
 195     description: |
 196       Phandle to aspeed,ast2500-scu compatible syscon alongside register
 197       offset and bit number to identify how the SIRQ polarity should be
 198       configured. One possible data source is the LPC/eSPI mode bit. Only
 199       applicable to aspeed,ast2500-vuart.
 200     deprecated: true
 201
 202   aspeed,lpc-io-reg:
 203     $ref: '/schemas/types.yaml#/definitions/uint32'
 204     description: |
 205       The VUART LPC address.  Only applicable to aspeed,ast2500-vuart.
 206
 207   aspeed,lpc-interrupts:
 208     $ref: "/schemas/types.yaml#/definitions/uint32-array"
 209     minItems: 2
 210     maxItems: 2
 211     description: |
 212       A 2-cell property describing the VUART SIRQ number and SIRQ
 213       polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH).  Only
 214       applicable to aspeed,ast2500-vuart.
 215
 216 required:
 217   - reg
 218   - interrupts
 219
 220 unevaluatedProperties: false
 221
 222 examples:
 223   - |
 224     serial@80230000 {
 225         compatible = "ns8250";
 226         reg = <0x80230000 0x100>;
 227         interrupts = <10>;
 228         reg-shift = <2>;
 229         clock-frequency = <48000000>;
 230     };
 231   - |
 232     #include <dt-bindings/gpio/gpio.h>
 233     serial@49042000 {
 234         compatible = "andestech,uart16550", "ns16550a";
 235         reg = <0x49042000 0x400>;
 236         interrupts = <80>;
 237         clock-frequency = <48000000>;
 238         cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
 239         rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
 240         dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
 241         dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
 242         dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
 243         rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 244     };
 245   - |
 246     #include <dt-bindings/clock/aspeed-clock.h>
 247     #include <dt-bindings/interrupt-controller/irq.h>
 248     serial@1e787000 {
 249         compatible = "aspeed,ast2500-vuart";
 250         reg = <0x1e787000 0x40>;
 251         reg-shift = <2>;
 252         interrupts = <8>;
 253         clocks = <&syscon ASPEED_CLK_APB>;
 254         no-loopback-test;
 255         aspeed,lpc-io-reg = <0x3f8>;
 256         aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 257     };
 258
 259 ...