1 # Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
4 $id: http://devicetree.org/schemas/serial/8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART (Universal Asynchronous Receiver/Transmitter) bindings
10 - devicetree@vger.kernel.org
13 - $ref: /schemas/serial.yaml#
16 - aspeed,sirq-polarity-sense
20 const: aspeed,ast2500-vuart
43 - required: [ clock-frequency ]
44 - required: [ clocks ]
54 - const: aspeed,ast2400-vuart
55 - const: aspeed,ast2500-vuart
56 - const: intel,xscale-uart
57 - const: mrvl,pxa-uart
58 - const: nuvoton,npcm750-uart
59 - const: nvidia,tegra20-uart
60 - const: nxp,lpc3220-uart
70 - opencores,uart16550-rtlsvn105
76 - cavium,octeon-3860-uart
77 - xlnx,xps-uart16550-2.00.b
80 - ns16550 # Deprecated, unless the FIFO really is broken
87 - const: ralink,rt2880-uart
89 - ns16550 # Deprecated, unless the FIFO really is broken
93 - mediatek,mt7622-btif
94 - mediatek,mt7623-btif
95 - const: mediatek,mtk-btif
97 - const: mrvl,mmp-uart
98 - const: intel,xscale-uart
101 - nvidia,tegra30-uart
102 - nvidia,tegra114-uart
103 - nvidia,tegra124-uart
104 - nvidia,tegra186-uart
105 - nvidia,tegra194-uart
106 - nvidia,tegra210-uart
107 - const: nvidia,tegra20-uart
115 clock-frequency: true
124 $ref: /schemas/types.yaml#definitions/uint32
125 description: The current active speed of the UART.
129 Offset to apply to the mapbase from the start of the registers.
132 description: Quantity to shift the register offsets by.
136 The size (in bytes) of the IO accesses that should be performed on the
137 device. There are some systems that require 32-bit accesses to the
138 UART (e.g. TI davinci).
143 Set to indicate that the port is in use by the OpenFirmware RTAS and
144 should not be registered.
149 Set to indicate that the port does not implement loopback test mode.
152 $ref: /schemas/types.yaml#definitions/uint32
153 description: The fifo size of the UART.
158 One way to enable automatic flow control support. The driver is
159 allowed to detect support for the capability even without this
163 $ref: /schemas/types.yaml#definitions/uint32
165 Specify the TX FIFO low water indication for parts with programmable
170 How long to pause uart rx when input overrun is encountered.
179 aspeed,sirq-polarity-sense:
180 $ref: /schemas/types.yaml#/definitions/phandle-array
182 Phandle to aspeed,ast2500-scu compatible syscon alongside register
183 offset and bit number to identify how the SIRQ polarity should be
184 configured. One possible data source is the LPC/eSPI mode bit. Only
185 applicable to aspeed,ast2500-vuart.
191 unevaluatedProperties: false
196 compatible = "ns8250";
197 reg = <0x80230000 0x100>;
200 clock-frequency = <48000000>;
203 #include <dt-bindings/gpio/gpio.h>
205 compatible = "andestech,uart16550", "ns16550a";
206 reg = <0x49042000 0x400>;
208 clock-frequency = <48000000>;
209 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
210 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
211 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
212 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
213 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
214 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
217 #include <dt-bindings/clock/aspeed-clock.h>
219 compatible = "aspeed,ast2500-vuart";
220 reg = <0x1e787000 0x40>;
223 clocks = <&syscon ASPEED_CLK_APB>;
225 aspeed,sirq-polarity-sense = <&syscon 0x70 25>;