1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
16 that is not widely used, the definitions of which are listed here:
18 hart: A hardware execution context, which contains all the state
19 mandated by the RISC-V ISA: a PC and some registers. This
20 terminology is designed to disambiguate software's view of execution
21 contexts from any particular microarchitectural implementation
22 strategy. For example, an Intel laptop containing one socket with
23 two cores, each of which has two hyperthreads, could be described as
27 - $ref: /schemas/cpu.yaml#
28 - $ref: extensions.yaml
57 - const: sifive,rocket0
59 - const: riscv # Simulator only
61 Identifies that the hart uses the RISC-V instruction set
62 and identifies the type of the hart.
66 Identifies the largest MMU address translation mode supported by
67 this hart. These values originate from the RISC-V Privileged
68 Specification document, available from
69 https://riscv.org/specifications/
70 $ref: /schemas/types.yaml#/definitions/string
78 riscv,cbom-block-size:
79 $ref: /schemas/types.yaml#/definitions/uint32
81 The blocksize in bytes for the Zicbom cache operations.
83 riscv,cbop-block-size:
84 $ref: /schemas/types.yaml#/definitions/uint32
86 The blocksize in bytes for the Zicbop cache operations.
88 riscv,cboz-block-size:
89 $ref: /schemas/types.yaml#/definitions/uint32
91 The blocksize in bytes for the Zicboz cache operations.
93 # RISC-V has multiple properties for cache op block sizes as the sizes
94 # differ between individual CBO extensions
95 cache-op-block-size: false
96 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
97 timebase-frequency: false
101 additionalProperties: false
102 description: Describes the CPU's local interrupt controller
109 const: riscv,cpu-intc
111 interrupt-controller: true
116 - interrupt-controller
119 $ref: /schemas/types.yaml#/definitions/phandle-array
123 List of phandles to idle state nodes supported
124 by this hart (see ./idle-states.yaml).
128 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
129 DMIPS/MHz, relative to highest capacity-dmips-mhz
139 riscv,isa-base: [ "riscv,isa-extensions" ]
140 riscv,isa-extensions: [ "riscv,isa-base" ]
143 - interrupt-controller
145 unevaluatedProperties: false
149 // Example 1: SiFive Freedom U540G Development Kit
151 #address-cells = <1>;
153 timebase-frequency = <1000000>;
155 clock-frequency = <0>;
156 compatible = "sifive,rocket0", "riscv";
158 i-cache-block-size = <64>;
159 i-cache-sets = <128>;
160 i-cache-size = <16384>;
162 riscv,isa-base = "rv64i";
163 riscv,isa-extensions = "i", "m", "a", "c";
165 cpu_intc0: interrupt-controller {
166 #interrupt-cells = <1>;
167 compatible = "riscv,cpu-intc";
168 interrupt-controller;
172 clock-frequency = <0>;
173 compatible = "sifive,rocket0", "riscv";
174 d-cache-block-size = <64>;
176 d-cache-size = <32768>;
180 i-cache-block-size = <64>;
182 i-cache-size = <32768>;
185 mmu-type = "riscv,sv39";
188 riscv,isa-base = "rv64i";
189 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
191 cpu_intc1: interrupt-controller {
192 #interrupt-cells = <1>;
193 compatible = "riscv,cpu-intc";
194 interrupt-controller;
200 // Example 2: Spike ISA Simulator with 1 Hart
202 #address-cells = <1>;
207 compatible = "riscv";
208 mmu-type = "riscv,sv48";
209 riscv,isa-base = "rv64i";
210 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
212 interrupt-controller {
213 #interrupt-cells = <1>;
214 interrupt-controller;
215 compatible = "riscv,cpu-intc";