Documentation/devicetree/bindings/riscv/cpus.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: RISC-V bindings for 'cpus' DT nodes
   8
   9 maintainers:
  10   - Paul Walmsley <paul.walmsley@sifive.com>
  11   - Palmer Dabbelt <palmer@sifive.com>
  12   - Conor Dooley <conor@kernel.org>
  13
  14 description: |
  15   This document uses some terminology common to the RISC-V community
  16   that is not widely used, the definitions of which are listed here:
  17
  18   hart: A hardware execution context, which contains all the state
  19   mandated by the RISC-V ISA: a PC and some registers.  This
  20   terminology is designed to disambiguate software's view of execution
  21   contexts from any particular microarchitectural implementation
  22   strategy.  For example, an Intel laptop containing one socket with
  23   two cores, each of which has two hyperthreads, could be described as
  24   having four harts.
  25
  26 properties:
  27   compatible:
  28     oneOf:
  29       - items:
  30           - enum:
  31               - sifive,rocket0
  32               - sifive,bullet0
  33               - sifive,e5
  34               - sifive,e7
  35               - sifive,e71
  36               - sifive,u74-mc
  37               - sifive,u54
  38               - sifive,u74
  39               - sifive,u5
  40               - sifive,u7
  41               - canaan,k210
  42           - const: riscv
  43       - items:
  44           - enum:
  45               - sifive,e51
  46               - sifive,u54-mc
  47           - const: sifive,rocket0
  48           - const: riscv
  49       - const: riscv    # Simulator only
  50     description:
  51       Identifies that the hart uses the RISC-V instruction set
  52       and identifies the type of the hart.
  53
  54   mmu-type:
  55     description:
  56       Identifies the MMU address translation mode used on this
  57       hart.  These values originate from the RISC-V Privileged
  58       Specification document, available from
  59       https://riscv.org/specifications/
  60     $ref: "/schemas/types.yaml#/definitions/string"
  61     enum:
  62       - riscv,sv32
  63       - riscv,sv39
  64       - riscv,sv48
  65       - riscv,none
  66
  67   riscv,cbom-block-size:
  68     $ref: /schemas/types.yaml#/definitions/uint32
  69     description:
  70       The blocksize in bytes for the Zicbom cache operations.
  71
  72   riscv,isa:
  73     description:
  74       Identifies the specific RISC-V instruction set architecture
  75       supported by the hart.  These are documented in the RISC-V
  76       User-Level ISA document, available from
  77       https://riscv.org/specifications/
  78
  79       While the isa strings in ISA specification are case
  80       insensitive, letters in the riscv,isa string must be all
  81       lowercase to simplify parsing.
  82     $ref: "/schemas/types.yaml#/definitions/string"
  83     pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
  84
  85   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
  86   timebase-frequency: false
  87
  88   interrupt-controller:
  89     type: object
  90     description: Describes the CPU's local interrupt controller
  91
  92     properties:
  93       '#interrupt-cells':
  94         const: 1
  95
  96       compatible:
  97         const: riscv,cpu-intc
  98
  99       interrupt-controller: true
 100
 101     required:
 102       - '#interrupt-cells'
 103       - compatible
 104       - interrupt-controller
 105
 106   cpu-idle-states:
 107     $ref: '/schemas/types.yaml#/definitions/phandle-array'
 108     items:
 109       maxItems: 1
 110     description: |
 111       List of phandles to idle state nodes supported
 112       by this hart (see ./idle-states.yaml).
 113
 114 required:
 115   - riscv,isa
 116   - interrupt-controller
 117
 118 additionalProperties: true
 119
 120 examples:
 121   - |
 122     // Example 1: SiFive Freedom U540G Development Kit
 123     cpus {
 124         #address-cells = <1>;
 125         #size-cells = <0>;
 126         timebase-frequency = <1000000>;
 127         cpu@0 {
 128                 clock-frequency = <0>;
 129                 compatible = "sifive,rocket0", "riscv";
 130                 device_type = "cpu";
 131                 i-cache-block-size = <64>;
 132                 i-cache-sets = <128>;
 133                 i-cache-size = <16384>;
 134                 reg = <0>;
 135                 riscv,isa = "rv64imac";
 136                 cpu_intc0: interrupt-controller {
 137                         #interrupt-cells = <1>;
 138                         compatible = "riscv,cpu-intc";
 139                         interrupt-controller;
 140                 };
 141         };
 142         cpu@1 {
 143                 clock-frequency = <0>;
 144                 compatible = "sifive,rocket0", "riscv";
 145                 d-cache-block-size = <64>;
 146                 d-cache-sets = <64>;
 147                 d-cache-size = <32768>;
 148                 d-tlb-sets = <1>;
 149                 d-tlb-size = <32>;
 150                 device_type = "cpu";
 151                 i-cache-block-size = <64>;
 152                 i-cache-sets = <64>;
 153                 i-cache-size = <32768>;
 154                 i-tlb-sets = <1>;
 155                 i-tlb-size = <32>;
 156                 mmu-type = "riscv,sv39";
 157                 reg = <1>;
 158                 riscv,isa = "rv64imafdc";
 159                 tlb-split;
 160                 cpu_intc1: interrupt-controller {
 161                         #interrupt-cells = <1>;
 162                         compatible = "riscv,cpu-intc";
 163                         interrupt-controller;
 164                 };
 165         };
 166     };
 167
 168   - |
 169     // Example 2: Spike ISA Simulator with 1 Hart
 170     cpus {
 171         #address-cells = <1>;
 172         #size-cells = <0>;
 173         cpu@0 {
 174                 device_type = "cpu";
 175                 reg = <0>;
 176                 compatible = "riscv";
 177                 riscv,isa = "rv64imafdc";
 178                 mmu-type = "riscv,sv48";
 179                 interrupt-controller {
 180                         #interrupt-cells = <1>;
 181                         interrupt-controller;
 182                         compatible = "riscv,cpu-intc";
 183                 };
 184         };
 185     };
 186 ...