1 UniPhier reset controller
8 - compatible: should be one of the following:
9 "socionext,uniphier-ld4-reset" - for LD4 SoC
10 "socionext,uniphier-pro4-reset" - for Pro4 SoC
11 "socionext,uniphier-sld8-reset" - for sLD8 SoC
12 "socionext,uniphier-pro5-reset" - for Pro5 SoC
13 "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC
14 "socionext,uniphier-ld11-reset" - for LD11 SoC
15 "socionext,uniphier-ld20-reset" - for LD20 SoC
16 "socionext,uniphier-pxs3-reset" - for PXs3 SoC
17 - #reset-cells: should be 1.
22 compatible = "socionext,uniphier-ld11-sysctrl",
23 "simple-mfd", "syscon";
24 reg = <0x61840000 0x4000>;
27 compatible = "socionext,uniphier-ld11-reset";
35 Media I/O (MIO) reset, SD reset
36 -------------------------------
39 - compatible: should be one of the following:
40 "socionext,uniphier-ld4-mio-reset" - for LD4 SoC
41 "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC
42 "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC
43 "socionext,uniphier-pro5-sd-reset" - for Pro5 SoC
44 "socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC
45 "socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO)
46 "socionext,uniphier-ld11-sd-reset" - for LD11 SoC (SD)
47 "socionext,uniphier-ld20-sd-reset" - for LD20 SoC
48 "socionext,uniphier-pxs3-sd-reset" - for PXs3 SoC
49 - #reset-cells: should be 1.
54 compatible = "socionext,uniphier-ld11-mioctrl",
55 "simple-mfd", "syscon";
56 reg = <0x59810000 0x800>;
59 compatible = "socionext,uniphier-ld11-mio-reset";
71 - compatible: should be one of the following:
72 "socionext,uniphier-ld4-peri-reset" - for LD4 SoC
73 "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC
74 "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC
75 "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC
76 "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC
77 "socionext,uniphier-ld11-peri-reset" - for LD11 SoC
78 "socionext,uniphier-ld20-peri-reset" - for LD20 SoC
79 "socionext,uniphier-pxs3-peri-reset" - for PXs3 SoC
80 - #reset-cells: should be 1.
85 compatible = "socionext,uniphier-ld11-perictrl",
86 "simple-mfd", "syscon";
87 reg = <0x59820000 0x200>;
90 compatible = "socionext,uniphier-ld11-peri-reset";
98 Analog signal amplifier reset
99 -----------------------------
102 - compatible: should be one of the following:
103 "socionext,uniphier-ld11-adamv-reset" - for LD11 SoC
104 "socionext,uniphier-ld20-adamv-reset" - for LD20 SoC
105 - #reset-cells: should be 1.
110 compatible = "socionext,uniphier-ld11-adamv",
111 "simple-mfd", "syscon";
112 reg = <0x57920000 0x1000>;
115 compatible = "socionext,uniphier-ld11-adamv-reset";
126 USB3 core reset belongs to USB3 glue layer. Before using the core reset,
127 it is necessary to control the clocks and resets to enable this layer.
128 These clocks and resets should be described in each property.
131 - compatible: Should be
132 "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC
133 "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC
134 "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC
135 "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC
136 - #reset-cells: Should be 1.
137 - reg: Specifies offset and length of the register set for the device.
138 - clocks: A list of phandles to the clock gate for USB3 glue layer.
139 According to the clock-names, appropriate clocks are required.
140 - clock-names: Should contain
141 "gio", "link" - for Pro4 SoC
143 - resets: A list of phandles to the reset control for USB3 glue layer.
144 According to the reset-names, appropriate resets are required.
145 - reset-names: Should contain
146 "gio", "link" - for Pro4 SoC
152 compatible = "socionext,uniphier-ld20-dwc3-glue",
154 #address-cells = <1>;
156 ranges = <0 0x65b00000 0x400>;
159 compatible = "socionext,uniphier-ld20-usb3-reset";
162 clock-names = "link";
163 clocks = <&sys_clk 14>;
164 reset-names = "link";
165 resets = <&sys_rst 14>;