1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,V2L} USBPHY Control
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 The RZ/G2L USBPHY Control mainly controls reset and power down of the
20 - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL
21 - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
22 - renesas,r9a07g054-usbphy-ctrl # RZ/V2L
23 - const: renesas,rzg2l-usbphy-ctrl
40 The phandle's argument in the reset specifier is the PHY reset associated
53 additionalProperties: false
57 #include <dt-bindings/clock/r9a07g044-cpg.h>
59 phyrst: usbphy-ctrl@11c40000 {
60 compatible = "renesas,r9a07g044-usbphy-ctrl",
61 "renesas,rzg2l-usbphy-ctrl";
62 reg = <0x11c40000 0x10000>;
63 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
64 resets = <&cpg R9A07G044_USB_PRESETN>;
65 power-domains = <&cpg>;