1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L USBPHY Control
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 The RZ/G2L USBPHY Control mainly controls reset and power down of the
20 - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
21 - const: renesas,rzg2l-usbphy-ctrl
38 The phandle's argument in the reset specifier is the PHY reset associated
51 additionalProperties: false
55 #include <dt-bindings/clock/r9a07g044-cpg.h>
57 phyrst: usbphy-ctrl@11c40000 {
58 compatible = "renesas,r9a07g044-usbphy-ctrl",
59 "renesas,rzg2l-usbphy-ctrl";
60 reg = <0x11c40000 0x10000>;
61 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
62 resets = <&cpg R9A07G044_USB_PRESETN>;
63 power-domains = <&cpg>;