1 Pistachio Reset Controller
2 =============================================================================
4 This binding describes a reset controller device that is used to enable and
5 disable individual IP blocks within the Pistachio SoC using "soft reset"
6 control bits found in the Pistachio SoC top level registers.
8 The actual action taken when soft reset is asserted is hardware dependent.
9 However, when asserted it may not be possible to access the hardware's
10 registers, and following an assert/deassert sequence the hardware's previous
11 state may no longer be valid.
13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
24 cr_periph: clk@18148000 {
25 compatible = "img,pistachio-cr-periph", "syscon", "simple-mfd";
26 reg = <0x18148000 0x1000>;
27 clocks = <&clk_periph PERIPH_CLK_SYS>;
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
37 Specifying reset control of devices
38 =======================================
40 Device nodes should specify the reset channel required in their "resets"
41 property, containing a phandle to the pistachio reset device node and an
42 index specifying which reset to use, as described in
43 Documentation/devicetree/bindings/reset/reset.txt.
47 spdif_out: spdif-out@18100d00 {
49 resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>;
54 Macro definitions for the supported resets can be found in:
55 include/dt-bindings/reset/pistachio-resets.h