1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: OMAP4+ Remoteproc Devices
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
15 other hardware accelerators, for achieving various system level goals.
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
19 caches, an Interrupt Controller, a Cache Controller etc.
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
22 sub-system. The DSP processor sub-system can contain any of the TI's C64x,
23 C66x or C67x family of DSP cores as the main execution unit. The IPU processor
24 sub-system usually contains either a Dual-Core Cortex-M3 or Dual-Core
27 Each remote processor sub-system is represented as a single DT node. Each node
28 has a number of required or optional properties that enable the OS running on
29 the host processor (MPU) to perform the device management of the remote
30 processor and to communicate with the remote processor. The various properties
31 can be classified as constant or variable. The constant properties are
32 dictated by the SoC and does not change from one board to another having the
33 same SoC. Examples of constant properties include 'iommus', 'reg'. The
34 variable properties are dictated by the system integration aspects such as
35 memory on the board, or configuration used within the corresponding firmware
36 image. Examples of variable properties include 'mboxes', 'memory-region',
37 'timers', 'watchdog-timers' etc.
53 phandles to OMAP IOMMU nodes, that need to be programmed
54 for this remote processor to access any external RAM memory or
55 other peripheral device address spaces. This property usually
56 has only a single phandle. Multiple phandles are used only in
57 cases where the sub-system has different ports for different
58 sub-modules within the processor sub-system (eg: DRA7 DSPs),
59 and need the same programming in both the MMUs.
65 OMAP Mailbox specifier denoting the sub-mailbox, to be used for
66 communication with the remote processor. The specifier format is
68 Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
69 This property should match with the sub-mailbox node used in
74 Main functional clock for the remote processor
78 Reset handles for the remote processor
82 Default name of the firmware to load to the remote processor.
84 # Optional properties:
85 # --------------------
86 # Some of these properties are mandatory on some SoCs, and some are optional
87 # depending on the configuration of the firmware image to be executed on the
88 # remote processor. The conditions are mentioned for each property.
90 # The following are the optional properties:
93 $ref: /schemas/types.yaml#/definitions/phandle
95 phandle to the reserved memory node to be associated
96 with the remoteproc device. The reserved memory node
97 can be a CMA memory node, and should be defined as
99 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
103 Address space for any remoteproc memories present on
104 the SoC. Should contain an entry for each value in
105 'reg-names'. These are mandatory for all DSP and IPU
106 processors that have them (OMAP4/OMAP5 DSPs do not have
111 Required names for each of the address spaces defined in
112 the 'reg' property. Expects the names from the following
113 list, in the specified order, each representing the corresponding
114 internal RAM memory region.
123 $ref: /schemas/types.yaml#/definitions/phandle-array
125 Should be a triple of the phandle to the System Control
126 Configuration region that contains the boot address
127 register, the register offset of the boot address
128 register within the System Control module, and the bit
129 shift within the register. This property is required for
130 all the DSP instances on OMAP4, OMAP5 and DRA7xx SoCs.
132 ti,autosuspend-delay-ms:
134 Custom autosuspend delay for the remoteproc in milliseconds.
135 Recommended values is preferable to be in the order of couple
136 of seconds. A negative value can also be used to disable the
137 autosuspend behavior.
140 $ref: /schemas/types.yaml#/definitions/phandle-array
142 One or more phandles to OMAP DMTimer nodes, that serve
143 as System/Tick timers for the OS running on the remote
144 processors. This will usually be a single timer if the
145 processor sub-system is running in SMP mode, or one per
146 core in the processor sub-system. This can also be used
147 to reserve specific timers to be dedicated to the
150 This property is mandatory on remote processors requiring
151 external tick wakeup, and to support Power Management
152 features. The timers to be used should match with the
153 timers used in the firmware image.
156 $ref: /schemas/types.yaml#/definitions/phandle-array
158 One or more phandles to OMAP DMTimer nodes, used to
159 serve as Watchdog timers for the processor cores. This
160 will usually be one per executing processor core, even
161 if the processor sub-system is running a SMP OS.
163 The timers to be used should match with the watchdog
164 timers used in the firmware image.
213 additionalProperties: false
218 //Example 1: OMAP4 DSP
220 /* DSP Reserved Memory node */
221 #include <dt-bindings/clock/omap4.h>
223 #address-cells = <1>;
226 dsp_memory_region: dsp-memory@98000000 {
227 compatible = "shared-dma-pool";
228 reg = <0x98000000 0x800000>;
236 compatible = "ti,omap4-dsp";
237 ti,bootreg = <&scm_conf 0x304 0>;
239 mboxes = <&mailbox &mbox_dsp>;
240 memory-region = <&dsp_memory_region>;
241 ti,timers = <&timer5>;
242 ti,watchdog-timers = <&timer6>;
243 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
244 resets = <&prm_tesla 0>, <&prm_tesla 1>;
245 firmware-name = "omap4-dsp-fw.xe64T";
251 //Example 2: OMAP5 IPU
253 /* IPU Reserved Memory node */
254 #include <dt-bindings/clock/omap5.h>
256 #address-cells = <2>;
259 ipu_memory_region: ipu-memory@95800000 {
260 compatible = "shared-dma-pool";
261 reg = <0 0x95800000 0 0x3800000>;
268 #address-cells = <1>;
272 compatible = "ti,omap5-ipu";
273 reg = <0x55020000 0x10000>;
276 mboxes = <&mailbox &mbox_ipu>;
277 memory-region = <&ipu_memory_region>;
278 ti,timers = <&timer3>, <&timer4>;
279 ti,watchdog-timers = <&timer9>, <&timer11>;
280 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
281 resets = <&prm_core 2>;
282 firmware-name = "omap5-ipu-fw.xem4";
288 //Example 3: DRA7xx/AM57xx DSP
290 /* DSP1 Reserved Memory node */
291 #include <dt-bindings/clock/dra7.h>
293 #address-cells = <2>;
296 dsp1_memory_region: dsp1-memory@99000000 {
297 compatible = "shared-dma-pool";
298 reg = <0x0 0x99000000 0x0 0x4000000>;
305 #address-cells = <1>;
309 compatible = "ti,dra7-dsp";
310 reg = <0x40800000 0x48000>,
313 reg-names = "l2ram", "l1pram", "l1dram";
314 ti,bootreg = <&scm_conf 0x55c 0>;
315 iommus = <&mmu0_dsp1>, <&mmu1_dsp1>;
316 mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
317 memory-region = <&dsp1_memory_region>;
318 ti,timers = <&timer5>;
319 ti,watchdog-timers = <&timer10>;
320 resets = <&prm_dsp1 0>;
321 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
322 firmware-name = "dra7-dsp1-fw.xe66";