1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI K3 R5F processor subsystems
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14 processor subsystems/clusters (R5FSS). The dual core cluster can be used
15 either in a LockStep mode providing safety/fault tolerance features or in a
16 Split mode providing two individual compute cores for doubling the compute
17 capacity on most SoCs. These are used together with other processors present
18 on the SoC to achieve various system level goals.
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
24 AM62 SoC family support a single R5F core only which runs Device Manager
25 firmware and can also be used as a remote processor with IPC communication.
27 Each Dual-Core R5F sub-system is represented as a single DTS node
28 representing the cluster, with a pair of child DT nodes representing
29 the individual R5F cores. Each node has a number of required or optional
30 properties that enable the OS running on the host processor to perform
31 the device management of the remote processor and to communicate with the
36 pattern: "^r5fss(@.*)?"
49 Should contain a phandle to a PM domain provider node and an args
50 specifier containing the R5FSS device id value.
61 Standard ranges definition providing address translations for
62 local R5F TCM address spaces to bus addresses.
64 # Optional properties:
65 # --------------------
68 $ref: /schemas/types.yaml#/definitions/uint32
70 Configuration Mode for the Dual R5F cores within the R5F cluster.
71 For most SoCs (AM65x, J721E, J7200, J721s2),
72 It should be either a value of 1 (LockStep mode) or 0 (Split mode) on
73 most SoCs (AM65x, J721E, J7200, J721s2), default is LockStep mode if
76 It should be either a value of 0 (Split mode) or 2 (Single-CPU mode) and
77 default is Split mode if omitted.
79 It should be set as 3 (Single-Core mode) which is also the default if
83 # R5F Processor Child Nodes:
84 # ==========================
90 The R5F Sub-System device node should define two R5F child nodes, each
91 node representing a TI instantiation of the Arm Cortex R5F core. There
92 are some specific integration differences for the IP like the usage of
93 a Region Address Translator (RAT) for translating the larger SoC bus
94 addresses into a 32-bit address space for the processor. For AM62x,
95 the R5F Sub-System device node should only define one R5F child node
96 as it has only one core available.
98 Each R5F core has an associated 64 KB of Tightly-Coupled Memory (TCM)
99 internal memories split between two banks - TCMA and TCMB (further
100 interleaved into two banks TCMB0 and TCMB1). These memories (also called
101 ATCM and BTCM) provide read/write performance on par with the core's L1
102 caches. Each of the TCMs can be enabled or disabled independently and
103 either of them can be configured to appear at that R5F's address 0x0.
105 The cores do not use an MMU, but has a Region Address Translator
106 (RAT) module that is accessible only from the R5Fs for providing
107 translations between 32-bit CPU addresses into larger system bus
108 addresses. Cache and memory access settings are provided through a
109 Memory Protection Unit (MPU), programmable only from the R5Fs.
111 $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
125 - description: Address and Size of the ATCM internal memory region
126 - description: Address and Size of the BTCM internal memory region
135 Should contain the phandle to the reset controller node managing the
136 local resets for this device, and a reset specifier.
141 Should contain the name of the default firmware image
142 file located on the firmware search path
144 # The following properties are mandatory for R5F Core0 in both LockStep and Split
145 # modes, and are mandatory for R5F Core1 _only_ in Split mode. They are unused for
146 # R5F Core1 in LockStep mode:
150 OMAP Mailbox specifier denoting the sub-mailbox, to be used for
151 communication with the remote processor. This property should match
152 with the sub-mailbox node used in the firmware image.
157 phandle to the reserved memory nodes to be associated with the
158 remoteproc device. There should be at least two reserved memory nodes
159 defined. The reserved memory nodes should be carveout nodes, and
160 should be defined with a "no-map" property as per the bindings in
161 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
165 - description: region used for dynamic DMA allocations like vrings and
167 - description: region reserved for firmware image sections
168 additionalItems: true
171 # Optional properties:
172 # --------------------
173 # The following properties are optional properties for each of the R5F cores:
176 $ref: /schemas/types.yaml#/definitions/uint32
179 R5F core configuration mode dictating if ATCM should be enabled. The
180 R5F address of ATCM is dictated by ti,loczrama property. Should be
181 either a value of 1 (enabled) or 0 (disabled), default is disabled
182 if omitted. Recommended to enable it for maximizing TCMs.
185 $ref: /schemas/types.yaml#/definitions/uint32
188 R5F core configuration mode dictating if BTCM should be enabled. The
189 R5F address of BTCM is dictated by ti,loczrama property. Should be
190 either a value of 1 (enabled) or 0 (disabled), default is enabled if
194 $ref: /schemas/types.yaml#/definitions/uint32
197 R5F core configuration mode dictating which TCM should appear at
198 address 0 (from core's view). Should be either a value of 1 (ATCM
199 at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
202 $ref: /schemas/types.yaml#/definitions/phandle-array
208 phandles to one or more reserved on-chip SRAM regions. The regions
209 should be defined as child nodes of the respective SRAM node, and
210 should be defined as per the generic bindings in,
211 Documentation/devicetree/bindings/sram/sram.yaml
223 unevaluatedProperties: false
266 additionalProperties: false
271 #address-cells = <2>;
274 mailbox0: mailbox-0 {
278 mailbox1: mailbox-1 {
283 compatible = "simple-bus";
284 #address-cells = <2>;
286 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
287 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
288 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
289 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>;
292 compatible = "simple-bus";
293 #address-cells = <2>;
295 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS */
296 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
297 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
298 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */
300 /* AM65x MCU R5FSS node */
301 mcu_r5fss0: r5fss@41000000 {
302 compatible = "ti,am654-r5fss";
303 power-domains = <&k3_pds 129>;
304 ti,cluster-mode = <1>;
305 #address-cells = <1>;
307 ranges = <0x41000000 0x00 0x41000000 0x20000>,
308 <0x41400000 0x00 0x41400000 0x20000>;
310 mcu_r5f0: r5f@41000000 {
311 compatible = "ti,am654-r5f";
312 reg = <0x41000000 0x00008000>,
313 <0x41010000 0x00008000>;
314 reg-names = "atcm", "btcm";
316 ti,sci-dev-id = <159>;
317 ti,sci-proc-ids = <0x01 0xFF>;
318 resets = <&k3_reset 159 1>;
319 firmware-name = "am65x-mcu-r5f0_0-fw";
320 ti,atcm-enable = <1>;
321 ti,btcm-enable = <1>;
323 mboxes = <&mailbox0 &mbox_mcu_r5fss0_core0>;
324 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
325 <&mcu_r5fss0_core0_memory_region>;
326 sram = <&mcu_r5fss0_core0_sram>;
329 mcu_r5f1: r5f@41400000 {
330 compatible = "ti,am654-r5f";
331 reg = <0x41400000 0x00008000>,
332 <0x41410000 0x00008000>;
333 reg-names = "atcm", "btcm";
335 ti,sci-dev-id = <245>;
336 ti,sci-proc-ids = <0x02 0xFF>;
337 resets = <&k3_reset 245 1>;
338 firmware-name = "am65x-mcu-r5f0_1-fw";
339 ti,atcm-enable = <1>;
340 ti,btcm-enable = <1>;
342 mboxes = <&mailbox1 &mbox_mcu_r5fss0_core1>;