1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI K3 R5F processor subsystems
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14 processor subsystems/clusters (R5FSS). The dual core cluster can be used
15 either in a LockStep mode providing safety/fault tolerance features or in a
16 Split mode providing two individual compute cores for doubling the compute
17 capacity on most SoCs. These are used together with other processors present
18 on the SoC to achieve various system level goals.
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
24 Each Dual-Core R5F sub-system is represented as a single DTS node
25 representing the cluster, with a pair of child DT nodes representing
26 the individual R5F cores. Each node has a number of required or optional
27 properties that enable the OS running on the host processor to perform
28 the device management of the remote processor and to communicate with the
33 pattern: "^r5fss(@.*)?"
45 Should contain a phandle to a PM domain provider node and an args
46 specifier containing the R5FSS device id value.
57 Standard ranges definition providing address translations for
58 local R5F TCM address spaces to bus addresses.
60 # Optional properties:
61 # --------------------
64 $ref: /schemas/types.yaml#/definitions/uint32
66 Configuration Mode for the Dual R5F cores within the R5F cluster.
67 Should be either a value of 1 (LockStep mode) or 0 (Split mode) on
68 most SoCs (AM65x, J721E, J7200, J721s2), default is LockStep mode if
69 omitted; and should be either a value of 0 (Split mode) or 2
70 (Single-CPU mode) on AM64x SoCs, default is Split mode if omitted.
72 # R5F Processor Child Nodes:
73 # ==========================
79 The R5F Sub-System device node should define two R5F child nodes, each
80 node representing a TI instantiation of the Arm Cortex R5F core. There
81 are some specific integration differences for the IP like the usage of
82 a Region Address Translator (RAT) for translating the larger SoC bus
83 addresses into a 32-bit address space for the processor.
85 Each R5F core has an associated 64 KB of Tightly-Coupled Memory (TCM)
86 internal memories split between two banks - TCMA and TCMB (further
87 interleaved into two banks TCMB0 and TCMB1). These memories (also called
88 ATCM and BTCM) provide read/write performance on par with the core's L1
89 caches. Each of the TCMs can be enabled or disabled independently and
90 either of them can be configured to appear at that R5F's address 0x0.
92 The cores do not use an MMU, but has a Region Address Translater
93 (RAT) module that is accessible only from the R5Fs for providing
94 translations between 32-bit CPU addresses into larger system bus
95 addresses. Cache and memory access settings are provided through a
96 Memory Protection Unit (MPU), programmable only from the R5Fs.
98 $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
111 - description: Address and Size of the ATCM internal memory region
112 - description: Address and Size of the BTCM internal memory region
121 Should contain the phandle to the reset controller node managing the
122 local resets for this device, and a reset specifier.
127 Should contain the name of the default firmware image
128 file located on the firmware search path
130 # The following properties are mandatory for R5F Core0 in both LockStep and Split
131 # modes, and are mandatory for R5F Core1 _only_ in Split mode. They are unused for
132 # R5F Core1 in LockStep mode:
136 OMAP Mailbox specifier denoting the sub-mailbox, to be used for
137 communication with the remote processor. This property should match
138 with the sub-mailbox node used in the firmware image.
143 phandle to the reserved memory nodes to be associated with the
144 remoteproc device. There should be at least two reserved memory nodes
145 defined. The reserved memory nodes should be carveout nodes, and
146 should be defined with a "no-map" property as per the bindings in
147 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
151 - description: region used for dynamic DMA allocations like vrings and
153 - description: region reserved for firmware image sections
154 additionalItems: true
157 # Optional properties:
158 # --------------------
159 # The following properties are optional properties for each of the R5F cores:
162 $ref: /schemas/types.yaml#/definitions/uint32
165 R5F core configuration mode dictating if ATCM should be enabled. The
166 R5F address of ATCM is dictated by ti,loczrama property. Should be
167 either a value of 1 (enabled) or 0 (disabled), default is disabled
168 if omitted. Recommended to enable it for maximizing TCMs.
171 $ref: /schemas/types.yaml#/definitions/uint32
174 R5F core configuration mode dictating if BTCM should be enabled. The
175 R5F address of BTCM is dictated by ti,loczrama property. Should be
176 either a value of 1 (enabled) or 0 (disabled), default is enabled if
180 $ref: /schemas/types.yaml#/definitions/uint32
183 R5F core configuration mode dictating which TCM should appear at
184 address 0 (from core's view). Should be either a value of 1 (ATCM
185 at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
188 $ref: /schemas/types.yaml#/definitions/phandle-array
194 phandles to one or more reserved on-chip SRAM regions. The regions
195 should be defined as child nodes of the respective SRAM node, and
196 should be defined as per the generic bindings in,
197 Documentation/devicetree/bindings/sram/sram.yaml
209 unevaluatedProperties: false
232 additionalProperties: false
237 #address-cells = <2>;
240 mailbox0: mailbox-0 {
244 mailbox1: mailbox-1 {
249 compatible = "simple-bus";
250 #address-cells = <2>;
252 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
253 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
254 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
255 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>;
258 compatible = "simple-bus";
259 #address-cells = <2>;
261 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS */
262 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
263 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
264 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */
266 /* AM65x MCU R5FSS node */
267 mcu_r5fss0: r5fss@41000000 {
268 compatible = "ti,am654-r5fss";
269 power-domains = <&k3_pds 129>;
270 ti,cluster-mode = <1>;
271 #address-cells = <1>;
273 ranges = <0x41000000 0x00 0x41000000 0x20000>,
274 <0x41400000 0x00 0x41400000 0x20000>;
276 mcu_r5f0: r5f@41000000 {
277 compatible = "ti,am654-r5f";
278 reg = <0x41000000 0x00008000>,
279 <0x41010000 0x00008000>;
280 reg-names = "atcm", "btcm";
282 ti,sci-dev-id = <159>;
283 ti,sci-proc-ids = <0x01 0xFF>;
284 resets = <&k3_reset 159 1>;
285 firmware-name = "am65x-mcu-r5f0_0-fw";
286 ti,atcm-enable = <1>;
287 ti,btcm-enable = <1>;
289 mboxes = <&mailbox0 &mbox_mcu_r5fss0_core0>;
290 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
291 <&mcu_r5fss0_core0_memory_region>;
292 sram = <&mcu_r5fss0_core0_sram>;
295 mcu_r5f1: r5f@41400000 {
296 compatible = "ti,am654-r5f";
297 reg = <0x41400000 0x00008000>,
298 <0x41410000 0x00008000>;
299 reg-names = "atcm", "btcm";
301 ti,sci-dev-id = <245>;
302 ti,sci-proc-ids = <0x02 0xFF>;
303 resets = <&k3_reset 245 1>;
304 firmware-name = "am65x-mcu-r5f0_1-fw";
305 ti,atcm-enable = <1>;
306 ti,btcm-enable = <1>;
308 mboxes = <&mailbox1 &mbox_mcu_r5fss0_core1>;