1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC7280 MSS Peripheral Image Loader
10 - Sibi Sankar <quic_sibis@quicinc.com>
13 This document describes the hardware for a component that loads and boots firmware
14 on the Qualcomm Technology Inc. SC7280 Modem Hexagon Core.
23 - description: MSS QDSP6 registers
24 - description: RMB registers
33 - description: MSA Stream 1
34 - description: MSA Stream 2
38 - description: Path leading to system memory
42 - description: Watchdog interrupt
43 - description: Fatal interrupt
44 - description: Ready interrupt
45 - description: Handover interrupt
46 - description: Stop acknowledge interrupt
47 - description: Shutdown acknowledge interrupt
60 - description: GCC MSS IFACE clock
61 - description: GCC MSS OFFLINE clock
62 - description: GCC MSS SNOC_AXI clock
63 - description: RPMH PKA clock
64 - description: RPMH XO clock
76 - description: CX power domain
77 - description: MSS power domain
86 - description: AOSS restart
87 - description: PDC reset
96 - description: MBA reserved region
97 - description: modem reserved region
100 $ref: /schemas/types.yaml#/definitions/string-array
102 - description: Name of MBA firmware
103 - description: Name of modem firmware
106 $ref: /schemas/types.yaml#/definitions/phandle-array
108 Halt registers are used to halt transactions of various sub-components
112 - description: phandle to TCSR_MUTEX registers
113 - description: offset to the Q6 halt register
114 - description: offset to the modem halt register
115 - description: offset to the nc halt register
116 - description: offset to the vq6 halt register
119 $ref: /schemas/types.yaml#/definitions/phandle-array
120 description: EXT registers are used for various power related functionality
123 - description: phandle to TCSR_REG registers
124 - description: offset to the force_clk_en register
125 - description: offset to the rscc_disable register
127 - description: phandle to TCSR_MUTEX registers
128 - description: offset to the axim1_clk_off register
129 - description: offset to the crypto_clk_off register
132 $ref: /schemas/types.yaml#/definitions/phandle-array
133 description: QACCEPT registers are used to bring up/down Q-channels
136 - description: phandle to TCSR_MUTEX registers
137 - description: offset to the mdm qaccept register
138 - description: offset to the cx qaccept register
139 - description: offset to the axi qaccept register
142 $ref: /schemas/types.yaml#/definitions/phandle
143 description: Reference to the AOSS side-channel message RAM.
146 $ref: /schemas/types.yaml#/definitions/phandle-array
147 description: States used by the AP to signal the Hexagon core
149 - description: Stop the modem
151 qcom,smem-state-names:
152 description: The names of the state bits used for SMP2P output
156 $ref: qcom,glink-edge.yaml#
157 unevaluatedProperties: false
159 Qualcomm G-Link subnode which represents communication edge, channels
160 and devices related to the DSP.
165 - description: IRQ from MSS to GLINK
169 - description: Mailbox for communication between APPS and MSS
197 - qcom,smem-state-names
200 additionalProperties: false
204 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
205 #include <dt-bindings/clock/qcom,rpmh.h>
206 #include <dt-bindings/interconnect/qcom,sc7280.h>
207 #include <dt-bindings/interrupt-controller/arm-gic.h>
208 #include <dt-bindings/mailbox/qcom-ipcc.h>
209 #include <dt-bindings/power/qcom-rpmpd.h>
210 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
211 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
213 remoteproc_mpss: remoteproc@4080000 {
214 compatible = "qcom,sc7280-mss-pil";
215 reg = <0x04080000 0x10000>, <0x04180000 0x48>;
216 reg-names = "qdsp6", "rmb";
218 iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
220 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
222 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
223 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
224 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
225 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
226 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
227 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
229 interrupt-names = "wdog", "fatal", "ready", "handover",
230 "stop-ack", "shutdown-ack";
232 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
233 <&gcc GCC_MSS_OFFLINE_AXI_CLK>,
234 <&gcc GCC_MSS_SNOC_AXI_CLK>,
235 <&rpmhcc RPMH_PKA_CLK>,
236 <&rpmhcc RPMH_CXO_CLK>;
237 clock-names = "iface", "offline", "snoc_axi", "pka", "xo";
239 power-domains = <&rpmhpd SC7280_CX>,
240 <&rpmhpd SC7280_MSS>;
241 power-domain-names = "cx", "mss";
243 memory-region = <&mba_mem>, <&mpss_mem>;
245 qcom,qmp = <&aoss_qmp>;
247 qcom,smem-states = <&modem_smp2p_out 0>;
248 qcom,smem-state-names = "stop";
250 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
251 <&pdc_reset PDC_MODEM_SYNC_RESET>;
252 reset-names = "mss_restart", "pdc_reset";
254 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
255 qcom,ext-regs = <&tcsr 0x10000 0x10004>, <&tcsr_mutex 0x26004 0x26008>;
256 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>;
259 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
260 IPCC_MPROC_SIGNAL_GLINK_QMP
261 IRQ_TYPE_EDGE_RISING>;
262 mboxes = <&ipcc IPCC_CLIENT_MPSS
263 IPCC_MPROC_SIGNAL_GLINK_QMP>;
265 qcom,remote-pid = <1>;