1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/remoteproc/qcom,qcs404-cdsp-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QCS404 CDSP Peripheral Image Loader
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 This document defines the binding for a component that loads and boots firmware
14 on the Qualcomm Technology Inc. CDSP (Compute DSP).
19 - qcom,qcs404-cdsp-pil
24 The base address and size of the qdsp6ss register
28 - description: Watchdog interrupt
29 - description: Fatal interrupt
30 - description: Ready interrupt
31 - description: Handover interrupt
32 - description: Stop acknowledge interrupt
44 - description: XO clock
45 - description: SWAY clock
46 - description: TBU clock
47 - description: BIMC clock
48 - description: AHB AON clock
49 - description: Q6SS SLAVE clock
50 - description: Q6SS MASTER clock
51 - description: Q6 AXIM clock
66 - description: CX power domain
70 - description: AOSS restart
78 description: Reference to the reserved-memory for the Hexagon core
81 $ref: /schemas/types.yaml#/definitions/phandle-array
83 Phandle reference to a syscon representing TCSR followed by the
84 three offsets within syscon for q6, modem and nc halt registers.
87 $ref: /schemas/types.yaml#/definitions/phandle-array
88 description: States used by the AP to signal the Hexagon core
90 - description: Stop the modem
92 qcom,smem-state-names:
93 description: The names of the state bits used for SMP2P output
110 - qcom,smem-state-names
112 additionalProperties: false
116 #include <dt-bindings/interrupt-controller/arm-gic.h>
117 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
118 #include <dt-bindings/power/qcom-rpmpd.h>
119 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
121 compatible = "qcom,qcs404-cdsp-pil";
122 reg = <0x00b00000 0x4040>;
124 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
125 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
126 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
127 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
128 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
129 interrupt-names = "wdog", "fatal", "ready",
130 "handover", "stop-ack";
132 clocks = <&xo_board>,
133 <&gcc GCC_CDSP_CFG_AHB_CLK>,
134 <&gcc GCC_CDSP_TBU_CLK>,
135 <&gcc GCC_BIMC_CDSP_CLK>,
136 <&turingcc TURING_WRAPPER_AON_CLK>,
137 <&turingcc TURING_Q6SS_AHBS_AON_CLK>,
138 <&turingcc TURING_Q6SS_AHBM_AON_CLK>,
139 <&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
149 power-domains = <&rpmhpd SDM845_CX>;
151 resets = <&gcc GCC_CDSP_RESTART>;
152 reset-names = "restart";
154 qcom,halt-regs = <&tcsr 0x19004>;
156 memory-region = <&cdsp_fw_mem>;
158 qcom,smem-states = <&cdsp_smp2p_out 0>;
159 qcom,smem-state-names = "stop";