1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/remoteproc/qcom,msm8996-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm MSM8996 MSS Peripheral Image Loader (and similar)
10 - Bjorn Andersson <andersson@kernel.org>
11 - Sibi Sankar <quic_sibis@quicinc.com>
14 MSS Peripheral Image Loader loads and boots firmware on the
15 Qualcomm Technology Inc. MSM8996 Modem Hexagon Core (and similar).
20 - qcom,msm8996-mss-pil
21 - qcom,msm8998-mss-pil
27 - description: MSS QDSP6 registers
28 - description: RMB registers
37 - description: MSA Stream 1
38 - description: MSA Stream 2
42 - description: Watchdog interrupt
43 - description: Fatal interrupt
44 - description: Ready interrupt
45 - description: Handover interrupt
46 - description: Stop acknowledge interrupt
47 - description: Shutdown acknowledge interrupt
68 - description: CX power domain
69 - description: MX power domain
70 - description: MSS power domain (only valid for qcom,sdm845-mss-pil)
77 - const: mss # only valid for qcom,sdm845-mss-pil
81 description: PLL supply
85 - description: AOSS restart
86 - description: PDC reset (only valid for qcom,sdm845-mss-pil)
92 - const: pdc_reset # only valid for qcom,sdm845-mss-pil
96 $ref: /schemas/types.yaml#/definitions/phandle
97 description: Reference to the AOSS side-channel message RAM.
100 $ref: /schemas/types.yaml#/definitions/phandle-array
101 description: States used by the AP to signal the Hexagon core
103 - description: Stop modem
105 qcom,smem-state-names:
106 description: Names of the states used by the AP to signal the Hexagon core
111 $ref: /schemas/types.yaml#/definitions/phandle-array
113 Halt registers are used to halt transactions of various sub-components
117 - description: phandle to TCSR syscon region
118 - description: offset to the Q6 halt register
119 - description: offset to the modem halt register
120 - description: offset to the nc halt register
124 - description: MBA reserved region
125 - description: Modem reserved region
126 - description: Metadata reserved region
129 $ref: /schemas/types.yaml#/definitions/string-array
131 - description: Name of MBA firmware
132 - description: Name of modem firmware
135 $ref: /schemas/remoteproc/qcom,smd-edge.yaml#
137 Qualcomm Shared Memory subnode which represents communication edge,
138 channels and devices related to the Modem.
139 unevaluatedProperties: false
142 $ref: /schemas/remoteproc/qcom,glink-edge.yaml#
144 Qualcomm G-Link subnode which represents communication edge, channels
145 and devices related to the Modem.
146 unevaluatedProperties: false
148 # Deprecated properties
160 additionalProperties: false
174 additionalProperties: false
180 Metadata reserved region
188 additionalProperties: false
205 - qcom,smem-state-names
211 const: qcom,msm8996-mss-pil
216 - description: GCC MSS IFACE clock
217 - description: GCC MSS BUS clock
218 - description: GCC MSS MEM clock
219 - description: RPM XO clock
220 - description: GCC MSS GPLL0 clock
221 - description: GCC MSS SNOC_AXI clock
222 - description: GCC MSS MNOC_AXI clock
223 - description: RPM QDSS clock
247 - qcom,msm8998-mss-pil
248 - qcom,sdm660-mss-pil
253 - description: GCC MSS IFACE clock
254 - description: GCC MSS BUS clock
255 - description: GCC MSS MEM clock
256 - description: GCC MSS GPLL0 clock
257 - description: GCC MSS SNOC_AXI clock
258 - description: GCC MSS MNOC_AXI clock
259 - description: RPMH QDSS clock
260 - description: RPMH XO clock
277 const: qcom,sdm845-mss-pil
290 - description: GCC MSS IFACE clock
291 - description: GCC MSS BUS clock
292 - description: GCC MSS MEM clock
293 - description: GCC MSS GPLL0 clock
294 - description: GCC MSS SNOC_AXI clock
295 - description: GCC MSS MNOC_AXI clock
296 - description: GCC MSS PRNG clock
297 - description: RPMH XO clock
324 # Fallbacks for deprecated properties
333 additionalProperties: false
337 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
338 #include <dt-bindings/clock/qcom,rpmh.h>
339 #include <dt-bindings/interrupt-controller/arm-gic.h>
340 #include <dt-bindings/power/qcom-rpmpd.h>
341 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
342 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
345 compatible = "qcom,sdm845-mss-pil";
346 reg = <0x04080000 0x408>, <0x04180000 0x48>;
347 reg-names = "qdsp6", "rmb";
349 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
350 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
351 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
352 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
353 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
354 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
355 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack",
358 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
359 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
360 <&gcc GCC_BOOT_ROM_AHB_CLK>,
361 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
362 <&gcc GCC_MSS_SNOC_AXI_CLK>,
363 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
364 <&gcc GCC_PRNG_AHB_CLK>,
365 <&rpmhcc RPMH_CXO_CLK>;
366 clock-names = "iface", "bus", "mem", "gpll0_mss",
367 "snoc_axi", "mnoc_axi", "prng", "xo";
369 power-domains = <&rpmhpd SDM845_CX>,
371 <&rpmhpd SDM845_MSS>;
372 power-domain-names = "cx", "mx", "mss";
374 memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>;
376 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
377 <&pdc_reset PDC_MODEM_SYNC_RESET>;
378 reset-names = "mss_restart", "pdc_reset";
380 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
382 qcom,qmp = <&aoss_qmp>;
384 qcom,smem-states = <&modem_smp2p_out 0>;
385 qcom,smem-state-names = "stop";
388 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
390 qcom,remote-pid = <1>;
391 mboxes = <&apss_shared 12>;