Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt

   1 Tegra SoC PWFM controller
   2
   3 Required properties:
   4 - compatible: Must be:
   5   - "nvidia,tegra20-pwm": for Tegra20
   6   - "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30
   7   - "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114
   8   - "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124
   9   - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132
  10   - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210
  11   - "nvidia,tegra186-pwm": for Tegra186
  12   - "nvidia,tegra194-pwm": for Tegra194
  13 - reg: physical base address and length of the controller's registers
  14 - #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
  15   the cells format.
  16 - clocks: Must contain one entry, for the module clock.
  17   See ../clocks/clock-bindings.txt for details.
  18 - resets: Must contain an entry for each entry in reset-names.
  19   See ../reset/reset.txt for details.
  20 - reset-names: Must include the following entries:
  21   - pwm
  22
  23 Optional properties:
  24 ============================
  25 In some of the interface like PWM based regulator device, it is required
  26 to configure the pins differently in different states, especially in suspend
  27 state of the system. The configuration of pin is provided via the pinctrl
  28 DT node as detailed in the pinctrl DT binding document
  29         Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
  30
  31 The PWM node will have following optional properties.
  32 pinctrl-names:  Pin state names. Must be "default" and "sleep".
  33 pinctrl-0:      phandle for the default/active state of pin configurations.
  34 pinctrl-1:      phandle for the sleep state of pin configurations.
  35
  36 Example:
  37
  38         pwm: pwm@7000a000 {
  39                 compatible = "nvidia,tegra20-pwm";
  40                 reg = <0x7000a000 0x100>;
  41                 #pwm-cells = <2>;
  42                 clocks = <&tegra_car 17>;
  43                 resets = <&tegra_car 17>;
  44                 reset-names = "pwm";
  45         };
  46
  47
  48 Example with the pin configuration for suspend and resume:
  49 =========================================================
  50 Suppose pin PE7 (On Tegra210) interfaced with the regulator device and
  51 it requires PWM output to be tristated when system enters suspend.
  52 Following will be DT binding to achieve this:
  53
  54 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
  55
  56         pinmux@700008d4 {
  57                 pwm_active_state: pwm_active_state {
  58                         pe7 {
  59                                 nvidia,pins = "pe7";
  60                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  61                         };
  62                 };
  63
  64                 pwm_sleep_state: pwm_sleep_state {
  65                         pe7 {
  66                                 nvidia,pins = "pe7";
  67                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  68                         };
  69                 };
  70         };
  71
  72         pwm@7000a000 {
  73                 /* Mandatory PWM properties */
  74                 pinctrl-names = "default", "sleep";
  75                 pinctrl-0 = <&pwm_active_state>;
  76                 pinctrl-1 = <&pwm_sleep_state>;
  77         };