Documentation/devicetree/bindings/power/mediatek,power-controller.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Mediatek Power Domains Controller
   8
   9 maintainers:
  10   - MandyJH Liu <mandyjh.liu@mediatek.com>
  11   - Matthias Brugger <mbrugger@suse.com>
  12
  13 description: |
  14   Mediatek processors include support for multiple power domains which can be
  15   powered up/down by software based on different application scenes to save power.
  16
  17   IP cores belonging to a power domain should contain a 'power-domains'
  18   property that is a phandle for SCPSYS node representing the domain.
  19
  20 properties:
  21   $nodename:
  22     pattern: '^power-controller(@[0-9a-f]+)?$'
  23
  24   compatible:
  25     enum:
  26       - mediatek,mt6795-power-controller
  27       - mediatek,mt8167-power-controller
  28       - mediatek,mt8173-power-controller
  29       - mediatek,mt8183-power-controller
  30       - mediatek,mt8186-power-controller
  31       - mediatek,mt8192-power-controller
  32       - mediatek,mt8195-power-controller
  33
  34   '#power-domain-cells':
  35     const: 1
  36
  37   '#address-cells':
  38     const: 1
  39
  40   '#size-cells':
  41     const: 0
  42
  43 patternProperties:
  44   "^power-domain@[0-9a-f]+$":
  45     $ref: "#/$defs/power-domain-node"
  46     patternProperties:
  47       "^power-domain@[0-9a-f]+$":
  48         $ref: "#/$defs/power-domain-node"
  49         patternProperties:
  50           "^power-domain@[0-9a-f]+$":
  51             $ref: "#/$defs/power-domain-node"
  52             patternProperties:
  53               "^power-domain@[0-9a-f]+$":
  54                 $ref: "#/$defs/power-domain-node"
  55                 unevaluatedProperties: false
  56             unevaluatedProperties: false
  57         unevaluatedProperties: false
  58     unevaluatedProperties: false
  59
  60 $defs:
  61   power-domain-node:
  62     type: object
  63     description: |
  64       Represents the power domains within the power controller node as documented
  65       in Documentation/devicetree/bindings/power/power-domain.yaml.
  66
  67     properties:
  68
  69       '#power-domain-cells':
  70         description:
  71           Must be 0 for nodes representing a single PM domain and 1 for nodes
  72           providing multiple PM domains.
  73
  74       '#address-cells':
  75         const: 1
  76
  77       '#size-cells':
  78         const: 0
  79
  80       reg:
  81         description: |
  82           Power domain index. Valid values are defined in:
  83               "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain.
  84               "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.
  85               "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
  86               "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
  87               "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
  88               "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
  89         maxItems: 1
  90
  91       clocks:
  92         description: |
  93           A number of phandles to clocks that need to be enabled during domain
  94           power-up sequencing.
  95
  96       clock-names:
  97         description: |
  98           List of names of clocks, in order to match the power-up sequencing
  99           for each power domain we need to group the clocks by name. BASIC
 100           clocks need to be enabled before enabling the corresponding power
 101           domain, and should not have a '-' in their name (i.e mm, mfg, venc).
 102           SUSBYS clocks need to be enabled before releasing the bus protection,
 103           and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
 104
 105           In order to follow properly the power-up sequencing, the clocks must
 106           be specified by order, adding first the BASIC clocks followed by the
 107           SUSBSYS clocks.
 108
 109       domain-supply:
 110         description: domain regulator supply.
 111
 112       mediatek,infracfg:
 113         $ref: /schemas/types.yaml#/definitions/phandle
 114         description: phandle to the device containing the INFRACFG register range.
 115
 116       mediatek,smi:
 117         $ref: /schemas/types.yaml#/definitions/phandle
 118         description: phandle to the device containing the SMI register range.
 119
 120     required:
 121       - reg
 122
 123 required:
 124   - compatible
 125
 126 additionalProperties: false
 127
 128 examples:
 129   - |
 130     #include <dt-bindings/clock/mt8173-clk.h>
 131     #include <dt-bindings/power/mt8173-power.h>
 132
 133     soc {
 134         #address-cells = <2>;
 135         #size-cells = <2>;
 136
 137         scpsys: syscon@10006000 {
 138             compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
 139             reg = <0 0x10006000 0 0x1000>;
 140
 141             spm: power-controller {
 142                 compatible = "mediatek,mt8173-power-controller";
 143                 #address-cells = <1>;
 144                 #size-cells = <0>;
 145                 #power-domain-cells = <1>;
 146
 147                 /* power domains of the SoC */
 148                 power-domain@MT8173_POWER_DOMAIN_VDEC {
 149                     reg = <MT8173_POWER_DOMAIN_VDEC>;
 150                     clocks = <&topckgen CLK_TOP_MM_SEL>;
 151                     clock-names = "mm";
 152                     #power-domain-cells = <0>;
 153                 };
 154                 power-domain@MT8173_POWER_DOMAIN_VENC {
 155                     reg = <MT8173_POWER_DOMAIN_VENC>;
 156                     clocks = <&topckgen CLK_TOP_MM_SEL>,
 157                              <&topckgen CLK_TOP_VENC_SEL>;
 158                     clock-names = "mm", "venc";
 159                     #power-domain-cells = <0>;
 160                 };
 161                 power-domain@MT8173_POWER_DOMAIN_ISP {
 162                     reg = <MT8173_POWER_DOMAIN_ISP>;
 163                     clocks = <&topckgen CLK_TOP_MM_SEL>;
 164                     clock-names = "mm";
 165                     #power-domain-cells = <0>;
 166                 };
 167                 power-domain@MT8173_POWER_DOMAIN_MM {
 168                     reg = <MT8173_POWER_DOMAIN_MM>;
 169                     clocks = <&topckgen CLK_TOP_MM_SEL>;
 170                     clock-names = "mm";
 171                     #power-domain-cells = <0>;
 172                     mediatek,infracfg = <&infracfg>;
 173                 };
 174                 power-domain@MT8173_POWER_DOMAIN_VENC_LT {
 175                     reg = <MT8173_POWER_DOMAIN_VENC_LT>;
 176                     clocks = <&topckgen CLK_TOP_MM_SEL>,
 177                              <&topckgen CLK_TOP_VENC_LT_SEL>;
 178                     clock-names = "mm", "venclt";
 179                     #power-domain-cells = <0>;
 180                 };
 181                 power-domain@MT8173_POWER_DOMAIN_AUDIO {
 182                     reg = <MT8173_POWER_DOMAIN_AUDIO>;
 183                     #power-domain-cells = <0>;
 184                 };
 185                 power-domain@MT8173_POWER_DOMAIN_USB {
 186                     reg = <MT8173_POWER_DOMAIN_USB>;
 187                     #power-domain-cells = <0>;
 188                 };
 189                 power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
 190                     reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
 191                     clocks = <&clk26m>;
 192                     clock-names = "mfg";
 193                     #address-cells = <1>;
 194                     #size-cells = <0>;
 195                     #power-domain-cells = <1>;
 196
 197                     power-domain@MT8173_POWER_DOMAIN_MFG_2D {
 198                         reg = <MT8173_POWER_DOMAIN_MFG_2D>;
 199                         #address-cells = <1>;
 200                         #size-cells = <0>;
 201                         #power-domain-cells = <1>;
 202
 203                         power-domain@MT8173_POWER_DOMAIN_MFG {
 204                             reg = <MT8173_POWER_DOMAIN_MFG>;
 205                             #power-domain-cells = <0>;
 206                             mediatek,infracfg = <&infracfg>;
 207                         };
 208                     };
 209                 };
 210             };
 211         };
 212     };