1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek Power Domains Controller
10 - Weiyi Lu <weiyi.lu@mediatek.com>
11 - Matthias Brugger <mbrugger@suse.com>
14 Mediatek processors include support for multiple power domains which can be
15 powered up/down by software based on different application scenes to save power.
17 IP cores belonging to a power domain should contain a 'power-domains'
18 property that is a phandle for SCPSYS node representing the domain.
22 const: power-controller
26 - mediatek,mt8167-power-controller
27 - mediatek,mt8173-power-controller
28 - mediatek,mt8183-power-controller
29 - mediatek,mt8186-power-controller
30 - mediatek,mt8192-power-controller
31 - mediatek,mt8195-power-controller
33 '#power-domain-cells':
43 "^power-domain@[0-9a-f]+$":
46 Represents the power domains within the power controller node as documented
47 in Documentation/devicetree/bindings/power/power-domain.yaml.
51 '#power-domain-cells':
53 Must be 0 for nodes representing a single PM domain and 1 for nodes
54 providing multiple PM domains.
64 Power domain index. Valid values are defined in:
65 "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.
66 "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
67 "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
68 "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
69 "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
74 A number of phandles to clocks that need to be enabled during domain
79 List of names of clocks, in order to match the power-up sequencing
80 for each power domain we need to group the clocks by name. BASIC
81 clocks need to be enabled before enabling the corresponding power
82 domain, and should not have a '-' in their name (i.e mm, mfg, venc).
83 SUSBYS clocks need to be enabled before releasing the bus protection,
84 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
86 In order to follow properly the power-up sequencing, the clocks must
87 be specified by order, adding first the BASIC clocks followed by the
91 description: domain regulator supply.
94 $ref: /schemas/types.yaml#/definitions/phandle
95 description: phandle to the device containing the INFRACFG register range.
98 $ref: /schemas/types.yaml#/definitions/phandle
99 description: phandle to the device containing the SMI register range.
102 "^power-domain@[0-9a-f]+$":
105 Represents a power domain child within a power domain parent node.
109 '#power-domain-cells':
111 Must be 0 for nodes representing a single PM domain and 1 for nodes
112 providing multiple PM domains.
125 A number of phandles to clocks that need to be enabled during domain
130 List of names of clocks, in order to match the power-up sequencing
131 for each power domain we need to group the clocks by name. BASIC
132 clocks need to be enabled before enabling the corresponding power
133 domain, and should not have a '-' in their name (i.e mm, mfg, venc).
134 SUSBYS clocks need to be enabled before releasing the bus protection,
135 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
137 In order to follow properly the power-up sequencing, the clocks must
138 be specified by order, adding first the BASIC clocks followed by the
142 description: domain regulator supply.
145 $ref: /schemas/types.yaml#/definitions/phandle
146 description: phandle to the device containing the INFRACFG register range.
149 $ref: /schemas/types.yaml#/definitions/phandle
150 description: phandle to the device containing the SMI register range.
153 "^power-domain@[0-9a-f]+$":
156 Represents a power domain child within a power domain parent node.
160 '#power-domain-cells':
162 Must be 0 for nodes representing a single PM domain and 1 for nodes
163 providing multiple PM domains.
176 A number of phandles to clocks that need to be enabled during domain
181 List of names of clocks, in order to match the power-up sequencing
182 for each power domain we need to group the clocks by name. BASIC
183 clocks need to be enabled before enabling the corresponding power
184 domain, and should not have a '-' in their name (i.e mm, mfg, venc).
185 SUSBYS clocks need to be enabled before releasing the bus protection,
186 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
188 In order to follow properly the power-up sequencing, the clocks must
189 be specified by order, adding first the BASIC clocks followed by the
193 description: domain regulator supply.
196 $ref: /schemas/types.yaml#/definitions/phandle
197 description: phandle to the device containing the INFRACFG register range.
200 $ref: /schemas/types.yaml#/definitions/phandle
201 description: phandle to the device containing the SMI register range.
206 additionalProperties: false
211 additionalProperties: false
216 additionalProperties: false
221 additionalProperties: false
225 #include <dt-bindings/clock/mt8173-clk.h>
226 #include <dt-bindings/power/mt8173-power.h>
229 #address-cells = <2>;
232 scpsys: syscon@10006000 {
233 compatible = "syscon", "simple-mfd";
234 reg = <0 0x10006000 0 0x1000>;
236 spm: power-controller {
237 compatible = "mediatek,mt8173-power-controller";
238 #address-cells = <1>;
240 #power-domain-cells = <1>;
242 /* power domains of the SoC */
243 power-domain@MT8173_POWER_DOMAIN_VDEC {
244 reg = <MT8173_POWER_DOMAIN_VDEC>;
245 clocks = <&topckgen CLK_TOP_MM_SEL>;
247 #power-domain-cells = <0>;
249 power-domain@MT8173_POWER_DOMAIN_VENC {
250 reg = <MT8173_POWER_DOMAIN_VENC>;
251 clocks = <&topckgen CLK_TOP_MM_SEL>,
252 <&topckgen CLK_TOP_VENC_SEL>;
253 clock-names = "mm", "venc";
254 #power-domain-cells = <0>;
256 power-domain@MT8173_POWER_DOMAIN_ISP {
257 reg = <MT8173_POWER_DOMAIN_ISP>;
258 clocks = <&topckgen CLK_TOP_MM_SEL>;
260 #power-domain-cells = <0>;
262 power-domain@MT8173_POWER_DOMAIN_MM {
263 reg = <MT8173_POWER_DOMAIN_MM>;
264 clocks = <&topckgen CLK_TOP_MM_SEL>;
266 #power-domain-cells = <0>;
267 mediatek,infracfg = <&infracfg>;
269 power-domain@MT8173_POWER_DOMAIN_VENC_LT {
270 reg = <MT8173_POWER_DOMAIN_VENC_LT>;
271 clocks = <&topckgen CLK_TOP_MM_SEL>,
272 <&topckgen CLK_TOP_VENC_LT_SEL>;
273 clock-names = "mm", "venclt";
274 #power-domain-cells = <0>;
276 power-domain@MT8173_POWER_DOMAIN_AUDIO {
277 reg = <MT8173_POWER_DOMAIN_AUDIO>;
278 #power-domain-cells = <0>;
280 power-domain@MT8173_POWER_DOMAIN_USB {
281 reg = <MT8173_POWER_DOMAIN_USB>;
282 #power-domain-cells = <0>;
284 power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
285 reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
288 #address-cells = <1>;
290 #power-domain-cells = <1>;
292 power-domain@MT8173_POWER_DOMAIN_MFG_2D {
293 reg = <MT8173_POWER_DOMAIN_MFG_2D>;
294 #address-cells = <1>;
296 #power-domain-cells = <1>;
298 power-domain@MT8173_POWER_DOMAIN_MFG {
299 reg = <MT8173_POWER_DOMAIN_MFG>;
300 #power-domain-cells = <0>;
301 mediatek,infracfg = <&infracfg>;