Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/power/fsl,imx-gpc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Freescale i.MX General Power Controller
   8
   9 maintainers:
  10   - Philipp Zabel <p.zabel@pengutronix.de>
  11
  12 description: |
  13   The i.MX6 General Power Control (GPC) block contains DVFS load tracking
  14   counters and Power Gating Control (PGC).
  15
  16   The power domains are generic power domain providers as documented in
  17   Documentation/devicetree/bindings/power/power-domain.yaml. They are
  18   described as subnodes of the power gating controller 'pgc' node of the GPC.
  19
  20   IP cores belonging to a power domain should contain a 'power-domains'
  21   property that is a phandle pointing to the power domain the device belongs
  22   to.
  23
  24 properties:
  25   compatible:
  26     enum:
  27       - fsl,imx6q-gpc
  28       - fsl,imx6qp-gpc
  29       - fsl,imx6sl-gpc
  30       - fsl,imx6sx-gpc
  31
  32   reg:
  33     maxItems: 1
  34
  35   interrupts:
  36     maxItems: 1
  37
  38   clocks:
  39     maxItems: 1
  40
  41   clock-names:
  42     const: ipg
  43
  44   pgc:
  45     type: object
  46     additionalProperties: false
  47     description: list of power domains provided by this controller.
  48
  49     properties:
  50       '#address-cells':
  51         const: 1
  52
  53       '#size-cells':
  54         const: 0
  55
  56     patternProperties:
  57       "power-domain@[0-9]$":
  58         type: object
  59         additionalProperties: false
  60
  61         properties:
  62
  63           '#power-domain-cells':
  64             const: 0
  65
  66           reg:
  67             description: |
  68               The following DOMAIN_INDEX values are valid for i.MX6Q:
  69                 ARM_DOMAIN     0
  70                 PU_DOMAIN      1
  71               The following additional DOMAIN_INDEX value is valid for i.MX6SL:
  72                 DISPLAY_DOMAIN 2
  73               The following additional DOMAIN_INDEX value is valid for i.MX6SX:
  74                 PCI_DOMAIN     3
  75             maxItems: 1
  76
  77           clocks:
  78             description: |
  79               A number of phandles to clocks that need to be enabled during domain
  80               power-up sequencing to ensure reset propagation into devices located
  81               inside this power domain.
  82             minItems: 1
  83             maxItems: 7
  84
  85           power-supply: true
  86
  87         required:
  88           - '#power-domain-cells'
  89           - reg
  90
  91     required:
  92       - '#address-cells'
  93       - '#size-cells'
  94
  95 required:
  96   - compatible
  97   - reg
  98   - interrupts
  99   - clocks
 100   - clock-names
 101   - pgc
 102
 103 additionalProperties: false
 104
 105 examples:
 106   - |
 107     #include <dt-bindings/clock/imx6qdl-clock.h>
 108     #include <dt-bindings/interrupt-controller/arm-gic.h>
 109
 110     gpc@20dc000 {
 111         compatible = "fsl,imx6q-gpc";
 112         reg = <0x020dc000 0x4000>;
 113         interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 114         clocks = <&clks IMX6QDL_CLK_IPG>;
 115         clock-names = "ipg";
 116
 117         pgc {
 118             #address-cells = <1>;
 119             #size-cells = <0>;
 120
 121             power-domain@0 {
 122                 reg = <0>;
 123                 #power-domain-cells = <0>;
 124             };
 125
 126             pd_pu: power-domain@1 {
 127                 reg = <1>;
 128                 #power-domain-cells = <0>;
 129                 power-supply = <&reg_pu>;
 130                 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
 131                          <&clks IMX6QDL_CLK_GPU3D_SHADER>,
 132                          <&clks IMX6QDL_CLK_GPU2D_CORE>,
 133                          <&clks IMX6QDL_CLK_GPU2D_AXI>,
 134                          <&clks IMX6QDL_CLK_OPENVG_AXI>,
 135                          <&clks IMX6QDL_CLK_VPU_AXI>;
 136             };
 137         };
 138     };