1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. SM8450 TLMM block
10 - Vinod Koul <vkoul@kernel.org>
13 This binding describes the Top Level Mode Multiplexer (TLMM) block found
14 in the SM8450 platform.
17 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
21 const: qcom,sm8450-tlmm
27 interrupt-controller: true
28 '#interrupt-cells': true
46 additionalProperties: false
51 - $ref: "#/$defs/qcom-sm8450-tlmm-state"
54 $ref: "#/$defs/qcom-sm8450-tlmm-state"
55 additionalProperties: false
58 qcom-sm8450-tlmm-state:
61 Pinctrl node's client devices use subnodes for desired pin configuration.
62 Client device subnodes use below standard properties.
67 List of gpio pins affected by the properties specified in this
71 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
72 - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
78 Specify the alternative function to be configured for the specified
80 enum: [ aon_cam, atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
81 cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
82 cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
83 ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1, gcc_gp2, gcc_gp3,
84 gpio, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1,
85 mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck,
86 mi2s0_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
87 mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
88 mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
89 mss_grfc7, mss_grfc8, mss_grfc9, nav, pcie0_clkreqn,
90 pcie1_clkreqn, phase_flag, pll_bist, pll_clk, pri_mi2s,
91 prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, qlink0_request,
92 qlink0_wmss, qlink1_enable, qlink1_request, qlink1_wmss,
93 qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1,
94 qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11,
95 qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, qup2,
96 qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4,
97 qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
98 sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
99 tgu_ch3, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
100 tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present,
101 uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset,
102 usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]
116 - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
120 pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
125 additionalProperties: false
129 #include <dt-bindings/interrupt-controller/arm-gic.h>
131 compatible = "qcom,sm8450-tlmm";
132 reg = <0x0f100000 0x300000>;
135 gpio-ranges = <&tlmm 0 0 211>;
136 interrupt-controller;
137 #interrupt-cells = <2>;
138 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;