1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. SM8350 TLMM block
10 - Vinod Koul <vkoul@kernel.org>
13 This binding describes the Top Level Mode Multiplexer (TLMM) block found
14 in the SM8350 platform.
17 - $ref: "pinctrl.yaml#"
18 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
22 const: qcom,sm8350-tlmm
28 interrupt-controller: true
29 '#interrupt-cells': true
31 gpio-reserved-ranges: true
40 additionalProperties: false
45 - $ref: "#/$defs/qcom-sm8350-tlmm-state"
48 $ref: "#/$defs/qcom-sm8350-tlmm-state"
49 additionalProperties: false
52 qcom-sm8350-tlmm-state:
55 Pinctrl node's client devices use subnodes for desired pin configuration.
56 Client device subnodes use below standard properties.
61 List of gpio pins affected by the properties specified in this
65 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$"
66 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
72 Specify the alternative function to be configured for the specified
75 enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
76 cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
77 cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
78 ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
79 gpio, ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
80 mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
81 mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck,
82 mi2s1_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
83 mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
84 mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
85 mss_grfc7, mss_grfc8, mss_grfc9, nav_gpio, pa_indicator,
86 pcie0_clkreqn, pcie1_clkreqn, phase_flag, pll_bist, pll_clk,
87 pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable,
88 qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
89 qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0,
90 qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10,
91 qup11, qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19,
92 qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5,
93 qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
94 sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
95 tgu_ch3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data,
96 uim0_present, uim0_reset, uim1_clk, uim1_data, uim1_present,
97 uim1_reset, usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]
112 - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
116 pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$"
121 additionalProperties: false
125 #include <dt-bindings/interrupt-controller/arm-gic.h>
127 compatible = "qcom,sm8350-tlmm";
128 reg = <0x0f100000 0x300000>;
129 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
132 interrupt-controller;
133 #interrupt-cells = <2>;
134 gpio-ranges = <&tlmm 0 0 203>;
136 gpio-wo-subnode-state {
141 uart-w-subnodes-state {