Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. SM8350 TLMM block
   8
   9 maintainers:
  10   - Vinod Koul <vkoul@kernel.org>
  11
  12 description: |
  13   This binding describes the Top Level Mode Multiplexer (TLMM) block found
  14   in the SM8350 platform.
  15
  16 allOf:
  17   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  18
  19 properties:
  20   compatible:
  21     const: qcom,sm8350-tlmm
  22
  23   reg:
  24     maxItems: 1
  25
  26   interrupts: true
  27   interrupt-controller: true
  28   '#interrupt-cells': true
  29   gpio-controller: true
  30   gpio-reserved-ranges: true
  31   '#gpio-cells': true
  32   gpio-ranges: true
  33   wakeup-parent: true
  34
  35 required:
  36   - compatible
  37   - reg
  38
  39 additionalProperties: false
  40
  41 patternProperties:
  42   '-state$':
  43     oneOf:
  44       - $ref: "#/$defs/qcom-sm8350-tlmm-state"
  45       - patternProperties:
  46           ".*":
  47             $ref: "#/$defs/qcom-sm8350-tlmm-state"
  48
  49 $defs:
  50   qcom-sm8350-tlmm-state:
  51     type: object
  52     description:
  53       Pinctrl node's client devices use subnodes for desired pin configuration.
  54       Client device subnodes use below standard properties.
  55     $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
  56
  57     properties:
  58       pins:
  59         description:
  60           List of gpio pins affected by the properties specified in this
  61           subnode.
  62         items:
  63           oneOf:
  64             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$"
  65             - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
  66         minItems: 1
  67         maxItems: 36
  68
  69       function:
  70         description:
  71           Specify the alternative function to be configured for the specified
  72           pins.
  73
  74         enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
  75                 cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
  76                 cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
  77                 ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
  78                 gpio, ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
  79                 mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
  80                 mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck,
  81                 mi2s1_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
  82                 mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
  83                 mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
  84                 mss_grfc7, mss_grfc8, mss_grfc9, nav_gpio, pa_indicator,
  85                 pcie0_clkreqn, pcie1_clkreqn, phase_flag, pll_bist, pll_clk,
  86                 pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable,
  87                 qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
  88                 qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0,
  89                 qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10,
  90                 qup11, qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19,
  91                 qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5,
  92                 qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
  93                 sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
  94                 tgu_ch3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data,
  95                 uim0_present, uim0_reset, uim1_clk, uim1_data, uim1_present,
  96                 uim1_reset, usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]
  97
  98
  99       bias-disable: true
 100       bias-pull-down: true
 101       bias-pull-up: true
 102       drive-strength: true
 103       input-enable: true
 104       output-high: true
 105       output-low: true
 106
 107     required:
 108       - pins
 109       - function
 110
 111     additionalProperties: false
 112
 113 examples:
 114   - |
 115         #include <dt-bindings/interrupt-controller/arm-gic.h>
 116         pinctrl@f100000 {
 117                 compatible = "qcom,sm8350-tlmm";
 118                 reg = <0x0f100000 0x300000>;
 119                 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 120                 gpio-controller;
 121                 #gpio-cells = <2>;
 122                 interrupt-controller;
 123                 #interrupt-cells = <2>;
 124                 gpio-ranges = <&tlmm 0 0 203>;
 125
 126                 gpio-wo-subnode-state {
 127                         pins = "gpio1";
 128                         function = "gpio";
 129                 };
 130
 131                 uart-w-subnodes-state {
 132                         rx {
 133                                 pins = "gpio18";
 134                                 function = "qup3";
 135                                 bias-pull-up;
 136                         };
 137
 138                         tx {
 139                                 pins = "gpio19";
 140                                 function = "qup3";
 141                                 bias-disable;
 142                         };
 143                 };
 144         };
 145 ...