Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. SM8250 TLMM block
   8
   9 maintainers:
  10   - Bjorn Andersson <bjorn.andersson@linaro.org>
  11
  12 description:
  13   Top Level Mode Multiplexer pin controller in the Qualcomm SM8250 SoC.
  14
  15 properties:
  16   compatible:
  17     const: qcom,sm8250-pinctrl
  18
  19   reg:
  20     maxItems: 3
  21
  22   reg-names:
  23     items:
  24       - const: west
  25       - const: south
  26       - const: north
  27
  28   interrupts:
  29     maxItems: 1
  30
  31   interrupt-controller: true
  32   "#interrupt-cells": true
  33   gpio-controller: true
  34   "#gpio-cells": true
  35   gpio-ranges: true
  36   wakeup-parent: true
  37
  38   gpio-reserved-ranges:
  39     minItems: 1
  40     maxItems: 90
  41
  42   gpio-line-names:
  43     maxItems: 180
  44
  45 patternProperties:
  46   "-state$":
  47     oneOf:
  48       - $ref: "#/$defs/qcom-sm8250-tlmm-state"
  49       - patternProperties:
  50           "-pins$":
  51             $ref: "#/$defs/qcom-sm8250-tlmm-state"
  52         additionalProperties: false
  53
  54 $defs:
  55   qcom-sm8250-tlmm-state:
  56     type: object
  57     description:
  58       Pinctrl node's client devices use subnodes for desired pin configuration.
  59       Client device subnodes use below standard properties.
  60     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  61     unevaluatedProperties: false
  62
  63     properties:
  64       pins:
  65         description:
  66           List of gpio pins affected by the properties specified in this
  67           subnode.
  68         items:
  69           oneOf:
  70             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
  71             - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
  72         minItems: 1
  73         maxItems: 36
  74
  75       function:
  76         description:
  77           Specify the alternative function to be configured for the specified
  78           pins.
  79
  80         enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c,
  81                 cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
  82                 cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
  83                 ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
  84                 ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
  85                 mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
  86                 mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
  87                 mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1,
  88                 pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset,
  89                 pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3,
  90                 qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14,
  91                 qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6,
  92                 qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41,
  93                 sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1,
  94                 tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data,
  95                 tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en,
  96                 tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ]
  97
  98     required:
  99       - pins
 100
 101 allOf:
 102   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
 103
 104 required:
 105   - compatible
 106   - reg
 107   - reg-names
 108
 109 additionalProperties: false
 110
 111 examples:
 112   - |
 113     #include <dt-bindings/interrupt-controller/arm-gic.h>
 114     pinctrl@1f00000 {
 115         compatible = "qcom,sm8250-pinctrl";
 116         reg = <0x0f100000 0x300000>,
 117               <0x0f500000 0x300000>,
 118               <0x0f900000 0x300000>;
 119         reg-names = "west", "south", "north";
 120         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 121         gpio-controller;
 122         #gpio-cells = <2>;
 123         interrupt-controller;
 124         #interrupt-cells = <2>;
 125         gpio-ranges = <&tlmm 0 0 181>; /* GPIOs + ufs_reset */
 126         wakeup-parent = <&pdc>;
 127     };