Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SM8250 SoC LPASS LPI TLMM
   8
   9 maintainers:
  10   - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
  11
  12 description:
  13   Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
  14   (LPASS) Low Power Island (LPI) of Qualcomm SM8250 SoC.
  15
  16 properties:
  17   compatible:
  18     const: qcom,sm8250-lpass-lpi-pinctrl
  19
  20   reg:
  21     maxItems: 2
  22
  23   clocks:
  24     items:
  25       - description: LPASS Core voting clock
  26       - description: LPASS Audio voting clock
  27
  28   clock-names:
  29     items:
  30       - const: core
  31       - const: audio
  32
  33   gpio-controller: true
  34
  35   "#gpio-cells":
  36     description: Specifying the pin number and flags, as defined in
  37       include/dt-bindings/gpio/gpio.h
  38     const: 2
  39
  40   gpio-ranges:
  41     maxItems: 1
  42
  43 patternProperties:
  44   "-state$":
  45     oneOf:
  46       - $ref: "#/$defs/qcom-sm8250-lpass-state"
  47       - patternProperties:
  48           "-pins$":
  49             $ref: "#/$defs/qcom-sm8250-lpass-state"
  50         additionalProperties: false
  51
  52 $defs:
  53   qcom-sm8250-lpass-state:
  54     type: object
  55     description:
  56       Pinctrl node's client devices use subnodes for desired pin configuration.
  57       Client device subnodes use below standard properties.
  58     $ref: /schemas/pinctrl/pincfg-node.yaml
  59
  60     properties:
  61       pins:
  62         description:
  63           List of gpio pins affected by the properties specified in this
  64           subnode.
  65         items:
  66           oneOf:
  67             - pattern: "^gpio([0-9]|1[0-3])$"
  68         minItems: 1
  69         maxItems: 14
  70
  71       function:
  72         enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
  73                 qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
  74                 dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
  75                 i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
  76                 dmic3_data, i2s2_data ]
  77         description:
  78           Specify the alternative function to be configured for the specified
  79           pins.
  80
  81       drive-strength:
  82         enum: [2, 4, 6, 8, 10, 12, 14, 16]
  83         default: 2
  84         description:
  85           Selects the drive strength for the specified pins, in mA.
  86
  87       slew-rate:
  88         enum: [0, 1, 2, 3]
  89         default: 0
  90         description: |
  91             0: No adjustments
  92             1: Higher Slew rate (faster edges)
  93             2: Lower Slew rate (slower edges)
  94             3: Reserved (No adjustments)
  95
  96       bias-pull-down: true
  97       bias-pull-up: true
  98       bias-bus-hold: true
  99       bias-disable: true
 100       input-enable: true
 101       output-high: true
 102       output-low: true
 103
 104     required:
 105       - pins
 106       - function
 107
 108     additionalProperties: false
 109
 110 allOf:
 111   - $ref: pinctrl.yaml#
 112
 113 required:
 114   - compatible
 115   - reg
 116   - clocks
 117   - clock-names
 118   - gpio-controller
 119   - "#gpio-cells"
 120   - gpio-ranges
 121
 122 additionalProperties: false
 123
 124 examples:
 125   - |
 126     #include <dt-bindings/sound/qcom,q6afe.h>
 127     lpi_tlmm: pinctrl@33c0000 {
 128         compatible = "qcom,sm8250-lpass-lpi-pinctrl";
 129         reg = <0x33c0000 0x20000>,
 130               <0x3550000 0x10000>;
 131         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
 132                  <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
 133         clock-names = "core", "audio";
 134         gpio-controller;
 135         #gpio-cells = <2>;
 136         gpio-ranges = <&lpi_tlmm 0 0 14>;
 137
 138         wsa-swr-active-state {
 139             clk-pins {
 140                 pins = "gpio10";
 141                 function = "wsa_swr_clk";
 142                 drive-strength = <2>;
 143                 slew-rate = <1>;
 144                 bias-disable;
 145             };
 146
 147             data-pins {
 148                 pins = "gpio11";
 149                 function = "wsa_swr_data";
 150                 drive-strength = <2>;
 151                 slew-rate = <1>;
 152             };
 153         };
 154
 155         tx-swr-sleep-clk-state {
 156             pins = "gpio0";
 157             function = "swr_tx_clk";
 158             drive-strength = <2>;
 159             bias-pull-down;
 160         };
 161     };