Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8150-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SM8150 TLMM pin controller
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11   - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  12
  13 description:
  14   Top Level Mode Multiplexer pin controller in Qualcomm SM8150 SoC.
  15
  16 properties:
  17   compatible:
  18     const: qcom,sm8150-pinctrl
  19
  20   reg:
  21     maxItems: 4
  22
  23   reg-names:
  24     items:
  25       - const: west
  26       - const: east
  27       - const: north
  28       - const: south
  29
  30   interrupts:
  31     maxItems: 1
  32
  33   interrupt-controller: true
  34   "#interrupt-cells": true
  35   gpio-controller: true
  36   "#gpio-cells": true
  37   gpio-ranges: true
  38   wakeup-parent: true
  39
  40   gpio-reserved-ranges:
  41     minItems: 1
  42     maxItems: 88
  43
  44   gpio-line-names:
  45     maxItems: 175
  46
  47 patternProperties:
  48   "-state$":
  49     oneOf:
  50       - $ref: "#/$defs/qcom-sm8150-tlmm-state"
  51       - patternProperties:
  52           "-pins$":
  53             $ref: "#/$defs/qcom-sm8150-tlmm-state"
  54         additionalProperties: false
  55
  56 $defs:
  57   qcom-sm8150-tlmm-state:
  58     type: object
  59     description:
  60       Pinctrl node's client devices use subnodes for desired pin configuration.
  61       Client device subnodes use below standard properties.
  62     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  63     unevaluatedProperties: false
  64
  65     properties:
  66       pins:
  67         description:
  68           List of gpio pins affected by the properties specified in this
  69           subnode.
  70         items:
  71           oneOf:
  72             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
  73             - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
  74         minItems: 1
  75         maxItems: 36
  76
  77       function:
  78         description:
  79           Specify the alternative function to be configured for the specified
  80           pins.
  81
  82         enum: [ adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
  83                 atest_char0, atest_char1, atest_char2, atest_char3, audio_ref,
  84                 atest_usb1, atest_usb2, atest_usb10, atest_usb11, atest_usb12,
  85                 atest_usb13, atest_usb20, atest_usb21, atest_usb22,
  86                 atest_usb23, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
  87                 cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
  88                 cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
  89                 ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd, emac_phy, emac_pps,
  90                 gcc_gp1, gcc_gp2, gcc_gp3, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s,
  91                 jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
  92                 mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator,
  93                 pci_e0, phase_flag, pll_bypassnl, pll_bist, pci_e1, pll_reset,
  94                 pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti,
  95                 qlink_request, qlink_enable, qspi0, qspi1, qspi2, qspi3,
  96                 qspi_clk, qspi_cs, qua_mi2s, qup0, qup1, qup2, qup3, qup4,
  97                 qup5, qup6, qup7, qup8, qup9, qup10, qup11, qup12, qup13,
  98                 qup14, qup15, qup16, qup17, qup18, qup19, qup_l4, qup_l5,
  99                 qup_l6, rgmii, sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu,
 100                 ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
 101                 tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, usb2phy_ac,
 102                 usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
 103                 wlan2_adc0, wlan2_adc1, wmss_reset ]
 104
 105     required:
 106       - pins
 107
 108 allOf:
 109   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
 110
 111 required:
 112   - compatible
 113   - reg
 114   - reg-names
 115
 116 additionalProperties: false
 117
 118 examples:
 119   - |
 120     #include <dt-bindings/interrupt-controller/arm-gic.h>
 121
 122     tlmm: pinctrl@3100000 {
 123         compatible = "qcom,sm8150-pinctrl";
 124         reg = <0x03100000 0x300000>,
 125               <0x03500000 0x300000>,
 126               <0x03900000 0x300000>,
 127               <0x03d00000 0x300000>;
 128         reg-names = "west", "east", "north", "south";
 129         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 130         gpio-ranges = <&tlmm 0 0 176>;
 131         gpio-controller;
 132         #gpio-cells = <2>;
 133         interrupt-controller;
 134         #interrupt-cells = <2>;
 135         wakeup-parent = <&pdc>;
 136
 137         qup-spi0-default-state {
 138             pins = "gpio0", "gpio1", "gpio2", "gpio3";
 139             function = "qup0";
 140             drive-strength = <6>;
 141             bias-disable;
 142         };
 143
 144         pcie1-default-state {
 145             perst-pins {
 146                 pins = "gpio102";
 147                 function = "gpio";
 148                 drive-strength = <2>;
 149                 bias-pull-down;
 150             };
 151
 152             clkreq-pins {
 153                 pins = "gpio103";
 154                 function = "pci_e1";
 155                 drive-strength = <2>;
 156                 bias-pull-up;
 157             };
 158
 159             wake-pins {
 160                 pins = "gpio104";
 161                 function = "gpio";
 162                 drive-strength = <2>;
 163                 bias-pull-up;
 164             };
 165         };
 166     };