Documentation/devicetree/bindings/pinctrl/qcom,sm7150-tlmm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm7150-tlmm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SM7150 TLMM pin controller
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11   - Danila Tikhonov <danila@jiaxyga.com>
  12
  13 description:
  14   Top Level Mode Multiplexer pin controller in Qualcomm SM7150 SoC.
  15
  16 allOf:
  17   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  18
  19 properties:
  20   compatible:
  21     const: qcom,sm7150-tlmm
  22
  23   reg:
  24     maxItems: 3
  25
  26   reg-names:
  27     items:
  28       - const: west
  29       - const: north
  30       - const: south
  31
  32   interrupts:
  33     maxItems: 1
  34
  35   interrupt-controller: true
  36   "#interrupt-cells": true
  37   gpio-controller: true
  38   "#gpio-cells": true
  39   gpio-ranges: true
  40   wakeup-parent: true
  41
  42   gpio-reserved-ranges:
  43     minItems: 1
  44     maxItems: 60
  45
  46   gpio-line-names:
  47     maxItems: 119
  48
  49 patternProperties:
  50   "-state$":
  51     oneOf:
  52       - $ref: "#/$defs/qcom-sm7150-tlmm-state"
  53       - patternProperties:
  54           "-pins$":
  55             $ref: "#/$defs/qcom-sm7150-tlmm-state"
  56         additionalProperties: false
  57
  58 $defs:
  59   qcom-sm7150-tlmm-state:
  60     type: object
  61     description:
  62       Pinctrl node's client devices use subnodes for desired pin configuration.
  63       Client device subnodes use below standard properties.
  64     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  65     unevaluatedProperties: false
  66
  67     properties:
  68       pins:
  69         description:
  70           List of gpio pins affected by the properties specified in this
  71           subnode.
  72         items:
  73           oneOf:
  74             - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
  75             - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
  76                       sdc2_cmd, sdc2_data, ufs_reset ]
  77         minItems: 1
  78         maxItems: 36
  79
  80       function:
  81         description:
  82           Specify the alternative function to be configured for the specified
  83           pins.
  84
  85         enum: [ gpio, adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens,
  86                 atest_tsens2, atest_usb1, atest_usb2, cam_mclk, cci_async,
  87                 cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
  88                 cci_timer4, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2,
  89                 ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0,
  90                 gp_pdm1, gp_pdm2, gps_tx, jitter_bist, ldo_en, ldo_update,
  91                 m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
  92                 mdp_vsync3, mss_lte, nav_pps_in, nav_pps_out, pa_indicator,
  93                 pci_e, phase_flag, pll_bist, pll_bypassnl, pll_reset, pri_mi2s,
  94                 pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_enable,
  95                 qlink_request, qua_mi2s, qup00, qup01, qup02, qup03, qup04,
  96                 qup10, qup11, qup12, qup13, qup14, qup15, sd_write, sdc40,
  97                 sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, ter_mi2s,
  98                 tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsif1_clk, tsif1_data,
  99                 tsif1_en, tsif1_error, tsif1_sync, tsif2_clk, tsif2_data,
 100                 tsif2_en, tsif2_error, tsif2_sync, uim1_clk, uim1_data,
 101                 uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present,
 102                 uim2_reset, uim_batt, usb_phy, vfr_1, vsense_trigger,
 103                 wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk,
 104                 wsa_data ]
 105
 106     required:
 107       - pins
 108
 109 required:
 110   - compatible
 111   - reg
 112   - reg-names
 113
 114 additionalProperties: false
 115
 116 examples:
 117   - |
 118     #include <dt-bindings/interrupt-controller/arm-gic.h>
 119
 120     tlmm: pinctrl@3500000 {
 121         compatible = "qcom,sm7150-tlmm";
 122         reg = <0x03500000 0x300000>,
 123               <0x03900000 0x300000>,
 124               <0x03d00000 0x300000>;
 125         reg-names = "west", "north", "south";
 126         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 127         gpio-ranges = <&tlmm 0 0 120>;
 128         gpio-controller;
 129         #gpio-cells = <2>;
 130         interrupt-controller;
 131         #interrupt-cells = <2>;
 132         wakeup-parent = <&pdc>;
 133
 134         gpio-wo-state {
 135             pins = "gpio1";
 136             function = "gpio";
 137         };
 138
 139         uart-w-state {
 140             rx-pins {
 141                 pins = "gpio44";
 142                 function = "qup12";
 143                 bias-pull-up;
 144             };
 145
 146             tx-pins {
 147                 pins = "gpio45";
 148                 function = "qup12";
 149                 bias-disable;
 150             };
 151         };
 152     };
 153 ...