Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-tlmm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. SM6115, SM4250 TLMM block
   8
   9 maintainers:
  10   - Iskren Chernev <iskren.chernev@gmail.com>
  11
  12 description:
  13   Top Level Mode Multiplexer pin controller in Qualcomm SM4250 and SM6115
  14   SoCs.
  15
  16 properties:
  17   compatible:
  18     const: qcom,sm6115-tlmm
  19
  20   reg:
  21     maxItems: 3
  22
  23   reg-names:
  24     items:
  25       - const: west
  26       - const: south
  27       - const: east
  28
  29   interrupts:
  30     maxItems: 1
  31
  32   interrupt-controller: true
  33   "#interrupt-cells": true
  34   gpio-controller: true
  35   "#gpio-cells": true
  36   gpio-ranges: true
  37   gpio-reserved-ranges: true
  38   wakeup-parent: true
  39
  40 patternProperties:
  41   "-state$":
  42     oneOf:
  43       - $ref: "#/$defs/qcom-sm6115-tlmm-state"
  44       - patternProperties:
  45           "-pins$":
  46             $ref: "#/$defs/qcom-sm6115-tlmm-state"
  47         additionalProperties: false
  48
  49 $defs:
  50   qcom-sm6115-tlmm-state:
  51     type: object
  52     description:
  53       Pinctrl node's client devices use subnodes for desired pin configuration.
  54       Client device subnodes use below standard properties.
  55     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  56     unevaluatedProperties: false
  57
  58     properties:
  59       pins:
  60         description:
  61           List of gpio pins affected by the properties specified in this
  62           subnode.
  63         items:
  64           oneOf:
  65             - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
  66             - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
  67                       sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
  68         minItems: 1
  69         maxItems: 36
  70
  71       function:
  72         description:
  73           Specify the alternative function to be configured for the specified
  74           pins.
  75
  76         enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c,
  77                 cci_timer, cri_trng, dac_calib, dbg_out, ddr_bist, ddr_pxi0,
  78                 ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
  79                 gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, jitter_bist,
  80                 mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, mpm_pwr, mss_lte,
  81                 m_voc, nav_gpio, pa_indicator, pbs, pbs_out, phase_flag,
  82                 pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti,
  83                 qdss_gpio, qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb,
  84                 sdc2_tb, sd_write, ssbi_wtr1, tgu, tsense_pwm, uim1_clk,
  85                 uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
  86                 uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger,
  87                 wlan1_adc0, elan1_adc1 ]
  88
  89     required:
  90       - pins
  91
  92 allOf:
  93   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  94
  95 required:
  96   - compatible
  97   - reg
  98   - reg-names
  99
 100 additionalProperties: false
 101
 102 examples:
 103   - |
 104     #include <dt-bindings/interrupt-controller/arm-gic.h>
 105     tlmm: pinctrl@500000 {
 106         compatible = "qcom,sm6115-tlmm";
 107         reg = <0x500000 0x400000>,
 108               <0x900000 0x400000>,
 109               <0xd00000 0x400000>;
 110         reg-names = "west", "south", "east";
 111         interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 112         gpio-controller;
 113         #gpio-cells = <2>;
 114         interrupt-controller;
 115         #interrupt-cells = <2>;
 116         gpio-ranges = <&tlmm 0 0 114>;
 117
 118         sdc2_on_state: sdc2-on-state {
 119             clk-pins {
 120                 pins = "sdc2_clk";
 121                 bias-disable;
 122                 drive-strength = <16>;
 123             };
 124
 125             cmd-pins {
 126                 pins = "sdc2_cmd";
 127                 bias-pull-up;
 128                 drive-strength = <10>;
 129             };
 130
 131             data-pins {
 132                 pins = "sdc2_data";
 133                 bias-pull-up;
 134                 drive-strength = <10>;
 135             };
 136
 137             sd-cd-pins {
 138                 pins = "gpio88";
 139                 function = "gpio";
 140                 bias-pull-up;
 141                 drive-strength = <2>;
 142             };
 143         };
 144     };