1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. SM6115, SM4250 TLMM block
10 - Iskren Chernev <iskren.chernev@gmail.com>
13 This binding describes the Top Level Mode Multiplexer block found in the
14 SM4250/6115 platforms.
18 const: qcom,sm6115-tlmm
31 description: Specifies the TLMM summary IRQ
34 interrupt-controller: true
38 Specifies the PIN numbers and Flags, as defined in defined in
39 include/dt-bindings/interrupt-controller/irq.h
45 description: Specifying the pin number and flags, as defined in
46 include/dt-bindings/gpio/gpio.h
52 gpio-reserved-ranges: true
56 #PIN CONFIGURATION NODES
60 - $ref: "#/$defs/qcom-sm6115-tlmm-state"
63 $ref: "#/$defs/qcom-sm6115-tlmm-state"
64 additionalProperties: false
67 qcom-sm6115-tlmm-state:
70 Pinctrl node's client devices use subnodes for desired pin configuration.
71 Client device subnodes use below standard properties.
76 List of gpio pins affected by the properties specified in this
80 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
81 - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
82 sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
88 Specify the alternative function to be configured for the specified
91 enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c,
92 cci_timer, cri_trng, dac_calib, dbg_out, ddr_bist, ddr_pxi0,
93 ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
94 gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, jitter_bist,
95 mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, mpm_pwr, mss_lte,
96 m_voc, nav_gpio, pa_indicator, pbs, pbs_out, phase_flag,
97 pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti,
98 qdss_gpio, qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb,
99 sdc2_tb, sd_write, ssbi_wtr1, tgu, tsense_pwm, uim1_clk,
100 uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
101 uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger,
102 wlan1_adc0, elan1_adc1 ]
105 enum: [2, 4, 6, 8, 10, 12, 14, 16]
108 Selects the drive strength for the specified pins, in mA.
124 - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
128 pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
133 additionalProperties: false
136 - $ref: "pinctrl.yaml#"
143 - interrupt-controller
149 additionalProperties: false
153 #include <dt-bindings/interrupt-controller/arm-gic.h>
154 tlmm: pinctrl@500000 {
155 compatible = "qcom,sm6115-tlmm";
156 reg = <0x500000 0x400000>,
159 reg-names = "west", "south", "east";
160 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
163 interrupt-controller;
164 #interrupt-cells = <2>;
165 gpio-ranges = <&tlmm 0 0 114>;
167 sdc2_on_state: sdc2-on-state {
171 drive-strength = <16>;
177 drive-strength = <10>;
183 drive-strength = <10>;
190 drive-strength = <2>;