1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. SC8180X TLMM block
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 This binding describes the Top Level Mode Multiplexer block found in the
17 - $ref: "pinctrl.yaml#"
18 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
22 const: qcom,sc8180x-tlmm
34 interrupt-controller: true
35 '#interrupt-cells': true
37 gpio-reserved-ranges: true
47 additionalProperties: false
52 - $ref: "#/$defs/qcom-sc8180x-tlmm-state"
55 $ref: "#/$defs/qcom-sc8180x-tlmm-state"
56 additionalProperties: false
59 qcom-sc8180x-tlmm-state:
62 Pinctrl node's client devices use subnodes for desired pin configuration.
63 Client device subnodes use below standard properties.
68 List of gpio pins affected by the properties specified in this
72 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$"
73 - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
79 Specify the alternative function to be configured for the specified
82 enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens,
83 atest_tsens2, atest_usb0, atest_usb1, atest_usb2, atest_usb3,
84 atest_usb4, audio_ref, btfm_slimbus, cam_mclk, cci_async,
85 cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
86 cci_timer4, cci_timer5, cci_timer6, cci_timer7, cci_timer8,
87 cci_timer9, cri_trng, dbg_out, ddr_bist, ddr_pxi, debug_hot,
88 dp_hot, edp_hot, edp_lcd, emac_phy, emac_pps, gcc_gp1, gcc_gp2,
89 gcc_gp3, gcc_gp4, gcc_gp5, gpio, gps, grfc, hs1_mi2s, hs2_mi2s,
90 hs3_mi2s, jitter_bist, lpass_slimbus, m_voc, mdp_vsync,
91 mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4,
92 mdp_vsync5, mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1,
93 pci_e2, pci_e3, phase_flag, pll_bist, pll_bypassnl, pll_reset,
94 pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss_gpio, qlink,
95 qspi0, qspi0_clk, qspi0_cs, qspi1, qspi1_clk, qspi1_cs,
96 qua_mi2s, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
97 qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
98 qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii, sd_write, sdc4,
99 sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu,
100 tsense_pwm1, tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
101 usb0_phy, usb1_phy, usb2phy_ac, vfr_1, vsense_trigger,
102 wlan1_adc, wlan2_adc, wmss_reset ]
116 - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
120 pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$"
125 additionalProperties: false
129 #include <dt-bindings/interrupt-controller/arm-gic.h>
131 compatible = "qcom,sc8180x-tlmm";
132 reg = <0x03100000 0x300000>,
133 <0x03500000 0x700000>,
134 <0x03d00000 0x300000>;
135 reg-names = "west", "east", "south";
136 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
139 interrupt-controller;
140 #interrupt-cells = <2>;
141 gpio-ranges = <&tlmm 0 0 190>;
143 gpio-wo-subnode-state {
148 uart-w-subnodes-state {