1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. SC7280 TLMM block
10 - Rajendra Nayak <rnayak@codeaurora.org>
13 This binding describes the Top Level Mode Multiplexer block found in the
18 const: qcom,sc7280-pinctrl
24 description: Specifies the TLMM summary IRQ
27 interrupt-controller: true
31 Specifies the PIN numbers and Flags, as defined in defined in
32 include/dt-bindings/interrupt-controller/irq.h
38 description: Specifying the pin number and flags, as defined in
39 include/dt-bindings/gpio/gpio.h
48 #PIN CONFIGURATION NODES
53 Pinctrl node's client devices use subnodes for desired pin configuration.
54 Client device subnodes use below standard properties.
55 $ref: "/schemas/pinctrl/pincfg-node.yaml"
60 List of gpio pins affected by the properties specified in this
64 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-4])$"
65 - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
66 sdc2_cmd, sdc2_data, ufs_reset ]
72 Specify the alternative function to be configured for the specified
75 enum: [ atest_char, atest_char0, atest_char1, atest_char2,
76 atest_char3, atest_usb0, atest_usb00, atest_usb01,
77 atest_usb02, atest_usb03, atest_usb1, atest_usb10,
78 atest_usb11, atest_usb12, atest_usb13, audio_ref,
79 cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
80 cci_timer2, cci_timer3, cci_timer4, cmu_rng0, cmu_rng1,
81 cmu_rng2, cmu_rng3, coex_uart1, cri_trng, cri_trng0,
82 cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, dp_hot,
83 dp_lcd, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
84 gpio, host2wlan_sol, ibi_i3c, jitter_bist, lpass_slimbus,
85 mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,
86 mdp_vsync4, mdp_vsync5, mi2s0_data0, mi2s0_data1, mi2s0_sck,
87 mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
88 mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mss_grfc0,
89 mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, mss_grfc2,
90 mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7,
91 mss_grfc8, mss_grfc9, nav_gpio0, nav_gpio1, nav_gpio2,
92 pa_indicator, pcie0_clkreqn, pcie1_clkreqn, phase_flag,
93 pll_bist, pll_bypassnl, pll_clk, pll_reset, pri_mi2s, prng_rosc,
94 qdss, qdss_cti, qlink0_enable, qlink0_request, qlink0_wmss,
95 qlink1_enable, qlink1_request, qlink1_wmss, qspi_clk, qspi_cs,
96 qspi_data, qup00, qup01, qup02, qup03, qup04, qup05, qup06, qup07,
97 qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
98 sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sd_write,
99 sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tsense_pwm1,
100 tsense_pwm2, uim0_clk, uim0_data, uim0_present, uim0_reset,
101 uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac,
102 usb_phy, vfr_0, vfr_1, vsense_trigger ]
105 enum: [2, 4, 6, 8, 10, 12, 14, 16]
108 Selects the drive strength for the specified pins, in mA.
124 additionalProperties: false
130 - interrupt-controller
136 additionalProperties: false
140 #include <dt-bindings/interrupt-controller/arm-gic.h>
141 tlmm: pinctrl@f000000 {
142 compatible = "qcom,sc7280-pinctrl";
143 reg = <0xf000000 0x1000000>;
144 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
147 interrupt-controller;
148 #interrupt-cells = <2>;
149 gpio-ranges = <&tlmm 0 0 175>;
150 wakeup-parent = <&pdc>;
152 qup_uart5_default: qup-uart5-pins {
153 pins = "gpio46", "gpio47";
155 drive-strength = <2>;