Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc7180-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SC7180 TLMM pin controller
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11   - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  12
  13 description:
  14   Top Level Mode Multiplexer pin controller in Qualcomm SC7180 SoC.
  15
  16 properties:
  17   compatible:
  18     const: qcom,sc7180-pinctrl
  19
  20   reg:
  21     maxItems: 3
  22
  23   reg-names:
  24     items:
  25       - const: west
  26       - const: north
  27       - const: south
  28
  29   interrupts:
  30     maxItems: 1
  31
  32   interrupt-controller: true
  33   "#interrupt-cells": true
  34   gpio-controller: true
  35   "#gpio-cells": true
  36   gpio-ranges: true
  37   wakeup-parent: true
  38
  39   gpio-reserved-ranges:
  40     minItems: 1
  41     maxItems: 60
  42
  43   gpio-line-names:
  44     maxItems: 119
  45
  46 patternProperties:
  47   "-state$":
  48     oneOf:
  49       - $ref: "#/$defs/qcom-sc7180-tlmm-state"
  50       - patternProperties:
  51           "-pins$":
  52             $ref: "#/$defs/qcom-sc7180-tlmm-state"
  53         additionalProperties: false
  54
  55 $defs:
  56   qcom-sc7180-tlmm-state:
  57     type: object
  58     description:
  59       Pinctrl node's client devices use subnodes for desired pin configuration.
  60       Client device subnodes use below standard properties.
  61     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  62     unevaluatedProperties: false
  63
  64     properties:
  65       pins:
  66         description:
  67           List of gpio pins affected by the properties specified in this
  68           subnode.
  69         items:
  70           oneOf:
  71             - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
  72             - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
  73                       sdc2_cmd, sdc2_data, ufs_reset ]
  74         minItems: 1
  75         maxItems: 36
  76
  77       function:
  78         description:
  79           Specify the alternative function to be configured for the specified
  80           pins.
  81
  82         enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0,
  83                 atest_char1, atest_char2, atest_char3, atest_tsens,
  84                 atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
  85                 atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,
  86                 atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,
  87                 cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,
  88                 cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0,
  89                 ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1,
  90                 gcc_gp2, gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx,
  91                 jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync,
  92                 mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1,
  93                 mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag, PLL_BIST,
  94                 pll_bypassnl, pll_reset, prng_rosc, qdss, qdss_cti,
  95                 qlink_enable, qlink_request, qspi_clk, qspi_cs, qspi_data,
  96                 qup00, qup01, qup02_i2c, qup02_uart, qup03, qup04_i2c,
  97                 qup04_uart, qup05, qup10, qup11_i2c, qup11_uart, qup12,
  98                 qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb, sdc2_tb,
  99                 sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
 100                 tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt, usb_phy, vfr_1,
 101                 _V_GPIO, _V_PPS_IN, _V_PPS_OUT, vsense_trigger, wlan1_adc0,
 102                 wlan1_adc1, wlan2_adc0, wlan2_adc1 ]
 103
 104     required:
 105       - pins
 106
 107 allOf:
 108   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
 109
 110 required:
 111   - compatible
 112   - reg
 113   - reg-names
 114
 115 additionalProperties: false
 116
 117 examples:
 118   - |
 119     #include <dt-bindings/interrupt-controller/arm-gic.h>
 120
 121     tlmm: pinctrl@3500000 {
 122         compatible = "qcom,sc7180-pinctrl";
 123         reg = <0x03500000 0x300000>,
 124               <0x03900000 0x300000>,
 125               <0x03d00000 0x300000>;
 126         reg-names = "west", "north", "south";
 127         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 128         gpio-controller;
 129         #gpio-cells = <2>;
 130         interrupt-controller;
 131         #interrupt-cells = <2>;
 132         gpio-ranges = <&tlmm 0 0 120>;
 133         wakeup-parent = <&pdc>;
 134
 135         dp_hot_plug_det: dp-hot-plug-det-state {
 136             pins = "gpio117";
 137             function = "dp_hot";
 138         };
 139
 140         qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
 141             spi-pins {
 142                 pins = "gpio53", "gpio54", "gpio55";
 143                 function = "qup15";
 144             };
 145
 146             cs-pins {
 147                 pins = "gpio56";
 148                 function = "gpio";
 149             };
 150         };
 151     };