Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,qcs404-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm QCS404 TLMM pin controller
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11   - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  12
  13 description:
  14   Top Level Mode Multiplexer pin controller in Qualcomm QCS404 SoC.
  15
  16 properties:
  17   compatible:
  18     const: qcom,qcs404-pinctrl
  19
  20   reg:
  21     maxItems: 3
  22
  23   reg-names:
  24     items:
  25       - const: south
  26       - const: north
  27       - const: east
  28
  29   interrupts:
  30     maxItems: 1
  31
  32   interrupt-controller: true
  33   "#interrupt-cells": true
  34   gpio-controller: true
  35   "#gpio-cells": true
  36   gpio-ranges: true
  37   wakeup-parent: true
  38
  39   gpio-reserved-ranges:
  40     minItems: 1
  41     maxItems: 60
  42
  43   gpio-line-names:
  44     maxItems: 120
  45
  46 patternProperties:
  47   "-state$":
  48     oneOf:
  49       - $ref: "#/$defs/qcom-qcs404-tlmm-state"
  50       - patternProperties:
  51           "-pins$":
  52             $ref: "#/$defs/qcom-qcs404-tlmm-state"
  53         additionalProperties: false
  54
  55 $defs:
  56   qcom-qcs404-tlmm-state:
  57     type: object
  58     description:
  59       Pinctrl node's client devices use subnodes for desired pin configuration.
  60       Client device subnodes use below standard properties.
  61     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  62     unevaluatedProperties: false
  63
  64     properties:
  65       pins:
  66         description:
  67           List of gpio pins affected by the properties specified in this
  68           subnode.
  69         items:
  70           oneOf:
  71             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9])$"
  72             - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
  73                       sdc2_cmd, sdc2_data, ufs_reset ]
  74         minItems: 1
  75         maxItems: 36
  76
  77       function:
  78         description:
  79           Specify the alternative function to be configured for the specified
  80           pins.
  81
  82         enum: [ gpio, adsp_ext, atest_char, atest_char0, atest_char1,
  83                 atest_char2, atest_char3, aud_cdc, audio_ts, bimc_dte0,
  84                 bimc_dte1, blsp_i2c0, blsp_i2c1, blsp_i2c3, blsp_i2c4,
  85                 blsp_i2c5, blsp_i2c_scl_a2, blsp_i2c_scl_b2, blsp_i2c_sda_a2,
  86                 blsp_i2c_sda_b2, blsp_spi0, blsp_spi2, blsp_spi3, blsp_spi4,
  87                 blsp_spi5, blsp_spi_clk_a1, blsp_spi_clk_b1, blsp_spi_cs_n_a1,
  88                 blsp_spi_cs_n_b1, blsp_spi_miso_a1, blsp_spi_miso_b1,
  89                 blsp_spi_mosi_a1, blsp_spi_mosi_b1, blsp_uart0, blsp_uart1,
  90                 blsp_uart2, blsp_uart3, blsp_uart5, blsp_uart_rx_a2,
  91                 blsp_uart_rx_b2, blsp_uart_tx_a2, blsp_uart_tx_b2, cri_trng,
  92                 cri_trng0, cri_trng1, dbg_out, dsd_clk_a, dsd_clk_b, ebi2_a,
  93                 ebi2_lcd, ebi_cdc, ebi_ch0, ext_lpass, ext_mclk0, ext_mclk1_a,
  94                 ext_mclk1_b, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a,
  95                 gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest,
  96                 gcc_tlmm, hdmi_ddc, hdmi_dtest, hdmi_lbk0, hdmi_lbk1,
  97                 hdmi_lbk2, hdmi_lbk3, hdmi_lbk4, hdmi_lbk5, hdmi_lbk6,
  98                 hdmi_lbk7, hdmi_lbk8, hdmi_lbk9, hdmi_pixel, hdmi_rcv, hdmi_tx,
  99                 i2s_1, i2s_2, i2s_3_data0_a, i2s_3_data0_b, i2s_3_data1_a,
 100                 i2s_3_data1_b, i2s_3_data2_a, i2s_3_data2_b, i2s_3_data3_a,
 101                 i2s_3_data3_b, i2s_3_sck_a, i2s_3_sck_b, i2s_3_ws_a,
 102                 i2s_3_ws_b, i2s_4, ir_in, ldo_en, ldo_update, mclk_in1,
 103                 mclk_in2, m_voc, nfc_dwl, nfc_irq, pcie_clk, pll_bist,
 104                 prng_rosc, pwm_led1, pwm_led10, pwm_led11, pwm_led12,
 105                 pwm_led13, pwm_led14, pwm_led15, pwm_led16, pwm_led17,
 106                 pwm_led18, pwm_led19, pwm_led2, pwm_led20, pwm_led21,
 107                 pwm_led22, pwm_led23, pwm_led24, pwm_led3, pwm_led4, pwm_led5,
 108                 pwm_led6, pwm_led7, pwm_led8, pwm_led9, qdss_cti_trig_in_a0,
 109                 qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
 110                 qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
 111                 qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
 112                 qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
 113                 qdss_tracedata_a, qdss_tracedata_b, rgb_clk, rgb_data0,
 114                 rgb_data1, rgb_data2, rgb_data3, rgb_data4, rgb_data5,
 115                 rgb_data6, rgb_data7, rgb_data_b0, rgb_data_b1, rgb_data_b2,
 116                 rgb_data_b3, rgb_data_b4, rgb_data_b5, rgb_data_b6,
 117                 rgb_data_b7, rgb_de, rgb_hsync, rgb_mdp, rgb_vsync, rgmi_dll1,
 118                 rgmi_dll2, rgmii_ck, rgmii_ctl, rgmii_int, rgmii_mdc,
 119                 rgmii_mdio, rgmii_rx, rgmii_tx, rgmii_wol, sd_write,
 120                 spdifrx_opt, spi_lcd, spkr_dac0, wlan1_adc0, wlan1_adc1,
 121                 wlan2_adc0, wlan2_adc1, wsa_en ]
 122
 123     required:
 124       - pins
 125
 126 allOf:
 127   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
 128
 129 required:
 130   - compatible
 131   - reg
 132
 133 additionalProperties: false
 134
 135 examples:
 136   - |
 137     #include <dt-bindings/interrupt-controller/arm-gic.h>
 138
 139     tlmm: pinctrl@1000000 {
 140         compatible = "qcom,qcs404-pinctrl";
 141         reg = <0x01000000 0x200000>,
 142               <0x01300000 0x200000>,
 143               <0x07b00000 0x200000>;
 144         reg-names = "south", "north", "east";
 145         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 146         gpio-ranges = <&tlmm 0 0 120>;
 147         gpio-controller;
 148         #gpio-cells = <2>;
 149         interrupt-controller;
 150         #interrupt-cells = <2>;
 151
 152
 153         blsp1-i2c1-default-state {
 154             pins = "gpio24", "gpio25";
 155             function = "blsp_i2c1";
 156         };
 157
 158         blsp1-i2c2-default-state {
 159             sda-pins {
 160                 pins = "gpio19";
 161                 function = "blsp_i2c_sda_a2";
 162             };
 163
 164             scl-pins {
 165                 pins = "gpio20";
 166                 function = "blsp_i2c_scl_a2";
 167             };
 168         };
 169     };