Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8909-tlmm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. MSM8909 TLMM block
   8
   9 maintainers:
  10   - Stephan Gerhold <stephan@gerhold.net>
  11
  12 description: |
  13   This binding describes the Top Level Mode Multiplexer (TLMM) block found
  14   in the MSM8909 platform.
  15
  16 allOf:
  17   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  18
  19 properties:
  20   compatible:
  21     const: qcom,msm8909-tlmm
  22
  23   reg:
  24     maxItems: 1
  25
  26   interrupts: true
  27   interrupt-controller: true
  28   '#interrupt-cells': true
  29   gpio-controller: true
  30   gpio-reserved-ranges: true
  31   '#gpio-cells': true
  32   gpio-ranges: true
  33   wakeup-parent: true
  34
  35 required:
  36   - compatible
  37   - reg
  38
  39 additionalProperties: false
  40
  41 patternProperties:
  42   '-state$':
  43     oneOf:
  44       - $ref: "#/$defs/qcom-msm8909-tlmm-state"
  45       - patternProperties:
  46           ".*":
  47             $ref: "#/$defs/qcom-msm8909-tlmm-state"
  48
  49 $defs:
  50   qcom-msm8909-tlmm-state:
  51     type: object
  52     description:
  53       Pinctrl node's client devices use subnodes for desired pin configuration.
  54       Client device subnodes use below standard properties.
  55     $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
  56
  57     properties:
  58       pins:
  59         description:
  60           List of gpio pins affected by the properties specified in this
  61           subnode.
  62         items:
  63           oneOf:
  64             - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-7])$"
  65             - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
  66                       sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1,
  67                       qdsd_data2, qdsd_data3 ]
  68         minItems: 1
  69         maxItems: 16
  70
  71       function:
  72         description:
  73           Specify the alternative function to be configured for the specified
  74           pins.
  75         enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
  76                 atest_char1, atest_char2, atest_char3, atest_combodac,
  77                 atest_gpsadc0, atest_gpsadc1, atest_wlan0, atest_wlan1,
  78                 bimc_dte0, bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3,
  79                 blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_spi1, blsp_spi1_cs1,
  80                 blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1,
  81                 blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3, blsp_spi3_cs1,
  82                 blsp_spi3_cs2, blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6,
  83                 blsp_uart1, blsp_uart2, blsp_uim1, blsp_uim2, cam_mclk,
  84                 cci_async, cci_timer0, cci_timer1, cci_timer2, cdc_pdm0,
  85                 dbg_out, dmic0_clk, dmic0_data, ebi0_wrcdc, ebi2_a, ebi2_lcd,
  86                 ext_lpass, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a,
  87                 gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gpio,
  88                 gsm0_tx, ldo_en, ldo_update, m_voc, mdp_vsync, modem_tsync,
  89                 nav_pps, nav_tsync, pa_indicator, pbs0, pbs1, pbs2,
  90                 pri_mi2s_data0_a, pri_mi2s_data0_b, pri_mi2s_data1_a,
  91                 pri_mi2s_data1_b, pri_mi2s_mclk_a, pri_mi2s_mclk_b,
  92                 pri_mi2s_sck_a, pri_mi2s_sck_b, pri_mi2s_ws_a, pri_mi2s_ws_b,
  93                 prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
  94                 pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
  95                 pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
  96                 qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
  97                 qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
  98                 qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a,
  99                 qdss_tracedata_a, qdss_tracedata_b, sd_write, sec_mi2s,
 100                 smb_int, ssbi0, ssbi1, uim1_clk, uim1_data, uim1_present,
 101                 uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
 102                 uim3_clk, uim3_data, uim3_present, uim3_reset, uim_batt,
 103                 wcss_bt, wcss_fm, wcss_wlan ]
 104
 105       bias-disable: true
 106       bias-pull-down: true
 107       bias-pull-up: true
 108       drive-strength: true
 109       input-enable: true
 110       output-high: true
 111       output-low: true
 112
 113     required:
 114       - pins
 115       - function
 116
 117     additionalProperties: false
 118
 119 examples:
 120   - |
 121         #include <dt-bindings/interrupt-controller/arm-gic.h>
 122
 123         pinctrl@1000000 {
 124                 compatible = "qcom,msm8909-tlmm";
 125                 reg = <0x1000000 0x300000>;
 126                 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 127                 gpio-controller;
 128                 #gpio-cells = <2>;
 129                 gpio-ranges = <&tlmm 0 0 117>;
 130                 interrupt-controller;
 131                 #interrupt-cells = <2>;
 132
 133                 gpio-wo-subnode-state {
 134                         pins = "gpio1";
 135                         function = "gpio";
 136                 };
 137
 138                 uart-w-subnodes-state {
 139                         rx {
 140                                 pins = "gpio4";
 141                                 function = "blsp_uart1";
 142                                 bias-pull-up;
 143                         };
 144
 145                         tx {
 146                                 pins = "gpio5";
 147                                 function = "blsp_uart1";
 148                                 bias-disable;
 149                         };
 150                 };
 151         };
 152 ...