Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,mdm9607-tlmm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. MDM9607 TLMM block
   8
   9 maintainers:
  10   - Konrad Dybcio <konrad.dybcio@somainline.org>
  11
  12 description:
  13   Top Level Mode Multiplexer pin controller in Qualcomm MDM9607 SoC.
  14
  15 allOf:
  16   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  17
  18 properties:
  19   compatible:
  20     const: qcom,mdm9607-tlmm
  21
  22   reg:
  23     maxItems: 1
  24
  25   interrupts:
  26     maxItems: 1
  27
  28   interrupt-controller: true
  29   "#interrupt-cells": true
  30   gpio-controller: true
  31   gpio-reserved-ranges: true
  32   "#gpio-cells": true
  33   gpio-ranges: true
  34   wakeup-parent: true
  35
  36 required:
  37   - compatible
  38   - reg
  39
  40 additionalProperties: false
  41
  42 patternProperties:
  43   "-state$":
  44     oneOf:
  45       - $ref: "#/$defs/qcom-mdm9607-tlmm-state"
  46       - additionalProperties: false
  47         patternProperties:
  48           ".*":
  49             $ref: "#/$defs/qcom-mdm9607-tlmm-state"
  50
  51 $defs:
  52   qcom-mdm9607-tlmm-state:
  53     type: object
  54     description:
  55       Pinctrl node's client devices use subnodes for desired pin configuration.
  56       Client device subnodes use below standard properties.
  57     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  58     unevaluatedProperties: false
  59
  60     properties:
  61       pins:
  62         description:
  63           List of gpio pins affected by the properties specified in this
  64           subnode.
  65         items:
  66           oneOf:
  67             - pattern: "^gpio([1-9]|[1-7][0-9]|80)$"
  68             - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
  69                       sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
  70                       qdsd_data3 ]
  71         minItems: 1
  72         maxItems: 16
  73
  74       function:
  75         description:
  76           Specify the alternative function to be configured for the specified
  77           pins.
  78
  79         enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
  80                 atest_char1, atest_char2, atest_char3,
  81                 atest_combodac_to_gpio_native, atest_gpsadc_dtest0_native,
  82                 atest_gpsadc_dtest1_native, atest_tsens, backlight_en_b,
  83                 bimc_dte0, bimc_dte1, blsp1_spi, blsp2_spi, blsp3_spi,
  84                 blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
  85                 blsp_i2c6, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4,
  86                 blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uart3,
  87                 blsp_uart4, blsp_uart5, blsp_uart6, blsp_uim1, blsp_uim2,
  88                 codec_int, codec_rst, coex_uart, cri_trng, cri_trng0,
  89                 cri_trng1, dbg_out, ebi0_wrcdc, ebi2_a, ebi2_a_d_8_b,
  90                 ebi2_lcd, ebi2_lcd_cs_n_b, ebi2_lcd_te_b, eth_irq, eth_rst,
  91                 gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b,
  92                 gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gmac_mdio,
  93                 gpio, gsm0_tx, lcd_rst, ldo_en, ldo_update, m_voc, modem_tsync,
  94                 nav_ptp_pps_in_a, nav_ptp_pps_in_b, nav_tsync_out_a,
  95                 nav_tsync_out_b, pa_indicator, pbs0, pbs1, pbs2,
  96                 pri_mi2s_data0_a, pri_mi2s_data1_a, pri_mi2s_mclk_a,
  97                 pri_mi2s_sck_a, pri_mi2s_ws_a, prng_rosc, ptp_pps_out_a,
  98                 ptp_pps_out_b, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
  99                 pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
 100                 pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
 101                 qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
 102                 qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
 103                 qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
 104                 qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, rcm_marker1,
 105                 rcm_marker2, sd_write, sec_mi2s, sensor_en, sensor_int2,
 106                 sensor_int3, sensor_rst, ssbi1, ssbi2, touch_rst, ts_int,
 107                 uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
 108                 uim2_data, uim2_present, uim2_reset, uim_batt, wlan_en1, ]
 109
 110     required:
 111       - pins
 112
 113 examples:
 114   - |
 115     #include <dt-bindings/interrupt-controller/arm-gic.h>
 116     tlmm: pinctrl@1000000 {
 117         compatible = "qcom,mdm9607-tlmm";
 118         reg = <0x01000000 0x300000>;
 119         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 120         gpio-controller;
 121         gpio-ranges = <&msmgpio 0 0 80>;
 122         #gpio-cells = <2>;
 123         interrupt-controller;
 124         #interrupt-cells = <2>;
 125     };