1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton WPCM450 pin control and GPIO
10 - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
14 const: nuvoton,wpcm450-pinctrl
26 # There are three kinds of subnodes:
27 # 1. a GPIO controller node for each GPIO bank
28 # 2. a pinmux node configures pin muxing for a group of pins (e.g. rmii2)
29 # 3. a pinconf node configures properties of a single pin
33 additionalProperties: false
36 Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18
37 GPIOs. Some GPIOs support interrupts.
49 interrupt-controller: true
57 The interrupts associated with this GPIO bank
65 $ref: pinmux-node.yaml#
70 One or more groups of pins to mux to a certain function
72 enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
73 hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo,
74 clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0,
75 fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11,
76 fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,
77 pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ]
80 The function that a group of pins is muxed to
81 enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
82 hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0,
83 dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc,
84 gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4,
85 fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15,
86 pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1,
87 hg2, hg3, hg4, hg5, hg6, hg7, gpio ]
93 additionalProperties: false
96 $ref: pincfg-node.yaml#
101 A list of pins to configure in certain ways, such as enabling
104 pattern: "^gpio1?[0-9]{1,2}$"
108 additionalProperties: false
114 additionalProperties: false
118 #include <dt-bindings/interrupt-controller/irq.h>
119 #include <dt-bindings/gpio/gpio.h>
120 pinctrl: pinctrl@b8003000 {
121 compatible = "nuvoton,wpcm450-pinctrl";
122 reg = <0xb8003000 0x1000>;
123 #address-cells = <1>;
130 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
131 <3 IRQ_TYPE_LEVEL_HIGH>,
132 <4 IRQ_TYPE_LEVEL_HIGH>;
140 pinmux_uid: mux-uid {
141 groups = "gspi", "sspi";
145 pinctrl_uid: cfg-uid {
147 input-debounce = <1>;
152 compatible = "gpio-keys";
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>;
159 gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;