1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,pinctrl-mt6795.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT6795 Pin Controller
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 - Sean Wang <sean.wang@kernel.org>
14 The Mediatek's Pin controller is used to control SoC pins.
18 const: mediatek,mt6795-pinctrl
24 Number of cells in GPIO specifier. Since the generic GPIO binding is used,
25 the amount of cells must be specified as 2. See the below
26 mentioned gpio binding representation for description of particular cells.
30 description: GPIO valid number range.
35 Physical address base for gpio base and eint registers.
43 interrupt-controller: true
49 description: The interrupt outputs to sysirq.
52 # PIN CONFIGURATION NODES
56 additionalProperties: false
60 additionalProperties: false
62 A pinctrl node should contain at least one subnodes representing the
63 pinctrl groups available on the machine. Each subnode will list the
64 pins it needs, and how they should be configured, with regard to muxer
65 configuration, pullups, drive strength, input enable/disable and
67 An example of using macro:
69 /* GPIO0 set as multifunction GPIO0 */
72 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
75 /* GPIO45 set as multifunction SDA0 */
78 pinmux = <PINMUX_GPIO45__FUNC_SDA0>;
82 $ref: "pinmux-node.yaml"
87 Integer array, represents gpio pin number and mux setting.
88 Supported pin number and mux varies for different SoCs, and are
89 defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h
93 enum: [2, 4, 6, 8, 10, 12, 14, 16]
98 - enum: [100, 101, 102, 103]
99 description: mt6795 pull down PUPD/R0/R1 type define value.
101 For normal pull down type, it is not necessary to specify R1R0
102 values; When pull down type is PUPD/R0/R1, adding R1R0 defines
103 will set different resistance values.
108 - enum: [100, 101, 102, 103]
109 description: mt6795 pull up PUPD/R0/R1 type define value.
111 For normal pull up type, it is not necessary to specify R1R0
112 values; When pull up type is PUPD/R0/R1, adding R1R0 defines
113 will set different resistance values.
125 input-schmitt-enable: true
127 input-schmitt-disable: true
129 mediatek,pull-up-adv:
131 Pull up setings for 2 pull resistors, R0 and R1. User can
132 configure those special pins. Valid arguments are described as below:
133 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
134 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
135 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
136 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
137 $ref: /schemas/types.yaml#/definitions/uint32
140 mediatek,pull-down-adv:
142 Pull down settings for 2 pull resistors, R0 and R1. User can
143 configure those special pins. Valid arguments are described as below:
144 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
145 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
146 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
147 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
148 $ref: /schemas/types.yaml#/definitions/uint32
155 - $ref: "pinctrl.yaml#"
162 - interrupt-controller
168 additionalProperties: false
172 #include <dt-bindings/interrupt-controller/arm-gic.h>
173 #include <dt-bindings/interrupt-controller/irq.h>
174 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
177 #address-cells = <2>;
180 pio: pinctrl@10005000 {
181 compatible = "mediatek,mt6795-pinctrl";
182 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
183 reg-names = "base", "eint";
186 gpio-ranges = <&pio 0 0 196>;
187 interrupt-controller;
188 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
189 #interrupt-cells = <2>;
193 pinmux = <PINMUX_GPIO45__FUNC_SDA0>,
194 <PINMUX_GPIO46__FUNC_SCL0>;
200 pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>,
201 <PINMUX_GPIO155__FUNC_MSDC0_DAT1>,
202 <PINMUX_GPIO156__FUNC_MSDC0_DAT2>,
203 <PINMUX_GPIO157__FUNC_MSDC0_DAT3>,
204 <PINMUX_GPIO158__FUNC_MSDC0_DAT4>,
205 <PINMUX_GPIO159__FUNC_MSDC0_DAT5>,
206 <PINMUX_GPIO160__FUNC_MSDC0_DAT6>,
207 <PINMUX_GPIO161__FUNC_MSDC0_DAT7>,
208 <PINMUX_GPIO162__FUNC_MSDC0_CMD>;
210 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
214 pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>;
215 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
219 pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>;
220 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;