1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6797-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT6797 Pin Controller Device Tree Bindings
10 - Sean Wang <sean.wang@kernel.org>
13 The MediaTek's MT6797 Pin controller is used to control SoC pins.
17 const: mediatek,mt6797-pinctrl
36 Number of cells in GPIO specifier. Since the generic GPIO
37 binding is used, the amount of cells must be specified as 2. See the below
38 mentioned gpio binding representation for description of particular cells.
40 interrupt-controller: true
58 additionalProperties: false
62 additionalProperties: false
64 A pinctrl node should contain at least one subnodes representing the
65 pinctrl groups available on the machine. Each subnode will list the
66 pins it needs, and how they should be configured, with regard to muxer
67 configuration, pullups, drive strength, input enable/disable and input
69 $ref: "/schemas/pinctrl/pincfg-node.yaml"
74 integer array, represents gpio pin number and mux setting.
75 Supported pin number and mux varies for different SoCs, and are
76 defined as macros in <soc>-pinfunc.h directly.
94 input-schmitt-enable: true
96 input-schmitt-disable: true
99 enum: [2, 4, 8, 12, 16]
104 mediatek,pull-up-adv:
106 Pull up setings for 2 pull resistors, R0 and R1. User can
107 configure those special pins. Valid arguments are described as below:
108 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
109 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
110 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
111 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
112 $ref: /schemas/types.yaml#/definitions/uint32
115 mediatek,pull-down-adv:
117 Pull down settings for 2 pull resistors, R0 and R1. User can
118 configure those special pins. Valid arguments are described as below:
119 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
120 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
121 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
122 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
123 $ref: /schemas/types.yaml#/definitions/uint32
128 An integer describing the steps for output level shifter duty
129 cycle when asserted (high pulse width adjustment). Valid arguments
131 $ref: /schemas/types.yaml#/definitions/uint32
135 An integer describing the steps for input level shifter duty cycle
136 when asserted (high pulse width adjustment). Valid arguments are
138 $ref: /schemas/types.yaml#/definitions/uint32
143 additionalProperties: false
147 #include <dt-bindings/interrupt-controller/irq.h>
148 #include <dt-bindings/interrupt-controller/arm-gic.h>
149 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
152 #address-cells = <2>;
155 pio: pinctrl@10005000 {
156 compatible = "mediatek,mt6797-pinctrl";
157 reg = <0 0x10005000 0 0x1000>,
158 <0 0x10002000 0 0x400>,
159 <0 0x10002400 0 0x400>,
160 <0 0x10002800 0 0x400>,
161 <0 0x10002C00 0 0x400>;
162 reg-names = "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt";
166 uart_pins_a: uart-0 {
168 pinmux = <MT6797_GPIO232__FUNC_URXD1>,
169 <MT6797_GPIO233__FUNC_UTXD1>;