1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT6779 Pin Controller
10 - Andy Teng <andy.teng@mediatek.com>
13 The pin controller node should be the child of a syscon node with the
15 - compatible: "syscon"
19 const: mediatek,mt6779-pinctrl
42 Number of cells in GPIO specifier. Since the generic GPIO
43 binding is used, the amount of cells must be specified as 2. See the below
44 mentioned gpio binding representation for description of particular cells.
50 GPIO valid number range.
52 interrupt-controller: true
57 Specifies the summary IRQ.
63 - $ref: "pinctrl.yaml#"
72 - interrupt-controller
79 additionalProperties: false
85 A pinctrl node should contain at least one subnodes representing the
86 pinctrl groups available on the machine. Each subnode will list the
87 pins it needs, and how they should be configured, with regard to muxer
88 configuration, pullups, drive strength, input enable/disable and input schmitt.
89 $ref: "/schemas/pinctrl/pincfg-node.yaml"
94 integer array, represents gpio pin number and mux setting.
95 Supported pin number and mux varies for different SoCs, and are defined
96 as macros in boot/dts/<soc>-pinfunc.h directly.
112 input-schmitt-enable: true
114 input-schmitt-disable: true
116 mediatek,pull-up-adv:
118 Pull up setings for 2 pull resistors, R0 and R1. User can
119 configure those special pins. Valid arguments are described as below:
120 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
121 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
122 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
123 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
124 $ref: /schemas/types.yaml#/definitions/uint32
127 mediatek,pull-down-adv:
129 Pull down settings for 2 pull resistors, R0 and R1. User can
130 configure those special pins. Valid arguments are described as below:
131 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
132 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
133 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
134 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
135 $ref: /schemas/types.yaml#/definitions/uint32
141 additionalProperties: false
143 additionalProperties: false
147 #include <dt-bindings/interrupt-controller/irq.h>
148 #include <dt-bindings/interrupt-controller/arm-gic.h>
149 #include <dt-bindings/pinctrl/mt6779-pinfunc.h>
152 #address-cells = <2>;
155 pio: pinctrl@10005000 {
156 compatible = "mediatek,mt6779-pinctrl";
157 reg = <0 0x10005000 0 0x1000>,
158 <0 0x11c20000 0 0x1000>,
159 <0 0x11d10000 0 0x1000>,
160 <0 0x11e20000 0 0x1000>,
161 <0 0x11e70000 0 0x1000>,
162 <0 0x11ea0000 0 0x1000>,
163 <0 0x11f20000 0 0x1000>,
164 <0 0x11f30000 0 0x1000>,
165 <0 0x1000b000 0 0x1000>;
166 reg-names = "gpio", "iocfg_rm",
167 "iocfg_br", "iocfg_lm",
168 "iocfg_lb", "iocfg_rt",
169 "iocfg_lt", "iocfg_tl",
173 gpio-ranges = <&pio 0 0 210>;
174 interrupt-controller;
175 #interrupt-cells = <2>;
176 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
178 mmc0_pins_default: mmc0-0 {
180 pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>,
181 <PINMUX_GPIO172__FUNC_MSDC0_DAT1>,
182 <PINMUX_GPIO169__FUNC_MSDC0_DAT2>,
183 <PINMUX_GPIO177__FUNC_MSDC0_DAT3>,
184 <PINMUX_GPIO170__FUNC_MSDC0_DAT4>,
185 <PINMUX_GPIO173__FUNC_MSDC0_DAT5>,
186 <PINMUX_GPIO171__FUNC_MSDC0_DAT6>,
187 <PINMUX_GPIO174__FUNC_MSDC0_DAT7>,
188 <PINMUX_GPIO167__FUNC_MSDC0_CMD>;
190 mediatek,pull-up-adv = <1>;
193 pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>;
194 mediatek,pull-down-adv = <2>;
197 pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>;
198 mediatek,pull-up-adv = <0>;
204 pinctrl-0 = <&mmc0_pins_default>;
205 pinctrl-names = "default";