1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT65xx Pin Controller
10 - Sean Wang <sean.wang@kernel.org>
13 The Mediatek's Pin controller is used to control SoC pins.
18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl
22 - mediatek,mt8127-pinctrl
23 - mediatek,mt8135-pinctrl
24 - mediatek,mt8167-pinctrl
25 - mediatek,mt8173-pinctrl
26 - mediatek,mt8516-pinctrl
32 $ref: /schemas/types.yaml#/definitions/flag
34 Specify the subnodes are using numbered pinmux to specify pins.
41 Number of cells in GPIO specifier. Since the generic GPIO
42 binding is used, the amount of cells must be specified as 2. See the below
43 mentioned gpio binding representation for description of particular cells.
46 $ref: /schemas/types.yaml#/definitions/phandle-array
52 Should be phandles of the syscfg node.
54 interrupt-controller: true
70 - $ref: "pinctrl.yaml#"
75 additionalProperties: false
79 additionalProperties: false
81 A pinctrl node should contain at least one subnodes representing the
82 pinctrl groups available on the machine. Each subnode will list the
83 pins it needs, and how they should be configured, with regard to muxer
84 configuration, pullups, drive strength, input enable/disable and input
86 $ref: "/schemas/pinctrl/pincfg-node.yaml"
91 integer array, represents gpio pin number and mux setting.
92 Supported pin number and mux varies for different SoCs, and are
93 defined as macros in <soc>-pinfunc.h directly.
99 Besides generic pinconfig options, it can be used as the pull up
100 settings for 2 pull resistors, R0 and R1. User can configure those
101 special pins. Some macros have been defined for this usage, such
102 as MTK_PUPD_SET_R1R0_00. See dt-bindings/pinctrl/mt65xx.h for
115 input-schmitt-enable: true
117 input-schmitt-disable: true
121 Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA,
122 etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments.
127 additionalProperties: false
131 #include <dt-bindings/interrupt-controller/irq.h>
132 #include <dt-bindings/interrupt-controller/arm-gic.h>
133 #include <dt-bindings/pinctrl/mt8135-pinfunc.h>
136 #address-cells = <2>;
139 syscfg_pctl_a: syscfg-pctl-a@10005000 {
140 compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
141 reg = <0 0x10005000 0 0x1000>;
144 syscfg_pctl_b: syscfg-pctl-b@1020c020 {
145 compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
146 reg = <0 0x1020C020 0 0x1000>;
150 compatible = "mediatek,mt8135-pinctrl";
151 reg = <0 0x1000B000 0 0x1000>;
152 mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
156 interrupt-controller;
157 #interrupt-cells = <2>;
158 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
162 i2c0_pins_a: i2c0-0 {
164 pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
165 <MT8135_PIN_101_SCL0__FUNC_SCL0>;
170 i2c1_pins_a: i2c1-0 {
172 pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
173 <MT8135_PIN_196_SCL1__FUNC_SCL1>;
174 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
178 i2c2_pins_a: i2c2-0 {
180 pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
185 pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
190 i2c3_pins_a: i2c3-0 {
192 pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
193 <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
194 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
198 pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
199 <MT8135_PIN_36_SDA3__FUNC_SDA3>;
201 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
205 pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
206 <MT8135_PIN_60_JTDI__FUNC_JTDI>;
207 drive-strength = <32>;